DefinitionBlock ( "acpi_dsdt.aml", //Output filename "DSDT", //Signature 0x1, //DSDT Revision "HP-MCD", //OEMID "GF DSDT", //TABLE ID 0x6040000 //OEM Revision ) { OperationRegion(MNVS, SystemMemory, 0x0f6fffac, 0x10) Field(MNVS, AnyAcc, Lock, Preserve) { OSYS, 16, CMAP, 8, CMBP, 8, FDCP, 8, LPTP, 8, Offset(0x7), THRT, 8 } Scope(\_PR_) { Processor(CPU0, 0, 0x1010, 0x6) { Name(XPCT, Package(0x2) { Buffer(0x11) {0x82, 0xc, 0x0, 0x1, 0x8, 0x0, 0x0, 0xb2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x79, 0x0 }, Buffer(0x11) {0x82, 0xc, 0x0, 0x1, 0x8, 0x0, 0x0, 0xb3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x79, 0x0 }, }) Name(XPSS, Package(0x2) { Package(0x6) { 0x270f, 0x0001869f, 0x03e7, 0x03e7, 0x99, 0x99, }, Package(0x6) { 0x270f, 0x0001869f, 0x03e7, 0x03e7, 0x99, 0x99, }, }) Method(XPPC) { If(THRT) { Return(0x1) } Else { Return(0x0) } } } } // _S0 - S0 SLP_TYP Value // // Evaluates to a package containing a DWORD value. // While the system is in the S0 state, it is in the // system working state. The behavior of this state // is defined as: // o The processors are in the Cx states. The // processor-complex context is maintained and // instructions are executed as defined by any of // these processor states. // o Dynamic RAM context is maintained and is // read/write by the processors. // o Devices states are individually managed by the // operating software and can be in any device // state (D0, D1, D2, or D3). // o Power Resources are in a state compatible with // the current device states. // // Transition into the S0 state from some system // sleeping state is automatic, and by virtue that // instructions are being executed OSPM, assumes the // system to be in the S0 state. The format is: // // Entry Type Description // ---------------------------------------- // 0 Integer [7:0] PM1a SLP_TYP // [15:8] PM1b SLP_TYP // [31:16] Reserved Name(_S0_, Package(0x3) { 0x0, 0x0, 0x0, }) // _S1 - S1 SLP_TYP Value // // Evaluates to a package containing a DWORD // value.While the system is in the S1 sleeping // state, its behavior is the following: // o The processors are not executing instructions. // The processor-complex context is maintained. // o Dynamic RAM context is maintained. // o Power Resources are in a state compatible with // the system S1 state. All Power Resources that // supply a System-Level reference of S0 are in // the OFF state. // o Devices states are compatible with the current // Power Resource states. Only devices that solely // reference Power Resources that are in the ON // state for a given device state can be in that // device state. In all other cases, the device is // in the D3 (off) state. // o Devices that are enabled to wake the system and // that can do so from their current device state // can initiate a hardware event that transitions // the system state to S0. This transition causes // the processor to continue execution where it // left off. // // To transition into the S1 state, the OSPM must // flush all processor caches. The format is: // // Entry Type Description // ---------------------------------------- // 0 Integer [7:0] PM1a SLP_TYP // [15:8] PM1b SLP_TYP // [31:16] Reserved Name(_S1_, Package(0x3) { 0x2, 0x2, 0x0, }) // _S3 - S3 SLP_TYP Value // // Evaluates to a package containing a DWORD // value.The S3 state is logically lower than the S2 // state and is assumed to conserve more power. The // behavior of this state is defined as follows: // // o The processors are not executing instructions. // The processor-complex context is not // maintained. // o Dynamic RAM context is maintained. // o Power Resources are in a state compatible with // the system S3 state.All Power Resources that // supply a System-Level reference of S0, S1, or // S2 are in the OFF state. // o Devices states are compatible with the current // Power Resource states. Only devices that solely // reference Power Resources that are in the ON // state for a given device state can be in that // device state. In all other cases, the device is // in the D3 (off) state. // o Devices that are enabled to wake the system and // that can do so from their current device state // can initiate a hardware event that transitions // the system state to S0. This transition causes // the processor to begin execution at its boot // location. The BIOS performs initialization of // core functions as necessary to exit an S3 state // and passes control to the firmware resume // vector. // From the software viewpoint, this state is // functionally the same as the S2 state. The // operational difference can be that some Power // Resources that could be left ON to be in the S2 // state might not be available to the S3 state. As // such, additional devices may need to be in a // logically lower D0, D1, D2, or D3 state for S3 // than S2. Similarly, some device wake events can // function in S2 but not S3. Because the processor // context can be lost while in the S3 state, the // transition to the S3 state requires that the // operating software flush all dirty cache to DRAM. // The format is: // // Entry Type Description // ---------------------------------------- // 0 Integer [7:0] PM1a SLP_TYP // [15:8] PM1b SLP_TYP // [31:16] Reserved Name(_S3_, Package(0x3) { 0x5, 0x5, 0x0, }) // _S4 - S4 SLP_TYP Value // // Evaluates to a package containing a DWORD // value.The state is logically lower than the S3 // state and is assumed to conserve more power. The // behavior of this state is defined as follows: // // o The processors are not executing instructions. // The processor-complex context is not // maintained. // o DRAM context is not maintained. // o Power Resources are in a state compatible with // the system S4 state. All Power Resources that // supply a System-Level reference of S0, S1, S2, // or S3 are in the OFF state. // o Devices states are compatible with the current // Power Resource states. In other words, all // devices are in the D3 state when the system // state is S4. // o Devices that are enabled to wake the system and // that can do so from their S4 device state can // initiate a hardware event that transitions the // system state to S0. This transition causes the // processor to begin execution at its boot // location. // // After OSPM has put the entire system state into // main memory, there are two ways that OSPM may // handle the next phase of the S4 state transition: // saving and restoring main memory. The first way // is to use the operating system's drivers to // access the disks and file system structures to // save a copy of memory to disk and then initiate // the hardware S4 sequence by setting the SLP_EN // register bit. When the system wakes, the firmware // performs a normal boot process and transfers // control to the OS via the Firmware_Waking_Vector // loader. The OS then restores the system's memory // and resumes execution.The alternate method for // entering the S4 state is to utilize the BIOS via // the S4BIOS transition. The BIOS uses firmware to // save a copy of memory to disk and then initiates // the hardware S4 sequence. When the system wakes, // the firmware restores memory from disk and wakes // OSPM by transferring control to the FACS waking // vector. The S4BIOS transition is optional, but // any system that supports this mechanism must // support entering the S4 state via the direct OS // mechanism. Thus the preferred mechanism for S4 // support is the direct OS mechanism as it provides // broader platform support. The alternate S4BIOS // transition provides a way to achieve S4 support // on operating systems that do not have support for // the direct method. The format is: // // Entry Type Description // ---------------------------------------- // 0 Integer [7:0] PM1a SLP_TYP // [15:8] PM1b SLP_TYP // [31:16] Reserved Name(_S4_, Package(0x3) { 0x6, 0x6, 0x0, }) // _S5 - S5 SLP_TYP Value // // Evaluates to a package containing a DWORD value. // The S5 state is similar to the S4 state except // that OSPM does not save any context. The system // is in the soft-off state and requires a complete // boot when awakened (BIOS and OS). Software uses a // different state value to distinguish between this // state and the S4 state to allow for initial boot // operations within the BIOS to distinguish whether // or not the boot is going to wake from a saved // memory image. OSPM will not disable wake events // before setting the SLP_EN bit when entering the // S5 sleeping state. This provides support for // remote management initiatives by enabling Remote // Power On (RPO) capability. This is a change from // ACPI 1.0 behavior. An ACPI 2.0-compliant OS must // provide an end-user accessible mechanism for // disabling all wake devices, with the exception of // the system power button, from a single point in // the user interface. The format is: // // Entry Type Description // ---------------------------------------- // 0 Integer [7:0] PM1a SLP_TYP // [15:8] PM1b SLP_TYP // [31:16] Reserved Name(_S5_, Package(0x3) { 0x7, 0x7, 0x0, }) OperationRegion(PORT, SystemIO, 0x80, 0x1) Field(PORT, ByteAcc, NoLock, Preserve) { P80H, 8 } Name(ECDY, 0x1) Name(RBIF, 0x0) Name(BSOK, 0x1) Name(OSTP, 0x0) Name(WAKT, 0x0) Name(DCKF, 0x0) // _PTS - Prepare To Sleep // // Executed by the OS at the beginning of the sleep // process for S1, S2, S3, S4, and orderly S5 // shutdown. Before OSPM notifies native device // drivers and prepares the system software for a // system sleeping state, it executes _PTS Thus, // _PTS can be executed a relatively long time // before actually entering the desired sleeping // state. In addition, OSPM can abort the sleeping // operation without notification to OSPM, in which // case another _PTS would occur some time before // the next attempt by OSPM to enter a sleeping // state. The _PTS method cannot modify the current // configuration or power state of any device in the // system. // // IN: Arg0 SleepState. 1=S1,2=S2,3=S3,4=S4,5=S5 // OUT: None // Method(_PTS, 1) { Store(\_SB_.PCI0.LPCB.EC0_.CSPR, DCKF) If(DCKF) { Store(0x1, \_SB_.PCI0.LPCB.COMA.SRSM) } If(LEqual(Arg0, 0x1)) { And(\_SB_.PCI0.LPCB.SIRQ, 0x7f, /* **** opcode has no effect */) Store(0x3, \_SB_.PCI0.USB0.U0EN) Store(0x3, \_SB_.PCI0.USB1.U1EN) Store(0x3, \_SB_.PCI0.USB2.U2EN) Store(0x1, \_SB_.PCI0.LPCB.RIEN) Store(\_SB_.PCI0.LPCB.RIS_, \_SB_.PCI0.LPCB.RIS_) Store(0x1, \_SB_.PCI0.LPCB.A97E) Store(\_SB_.PCI0.LPCB.A97S, \_SB_.PCI0.LPCB.A97S) Store(0x1, \_SB_.PCI0.PCIB.MIN1.MPME) Store(\_SB_.PCI0.PCIB.MIN1.MPMS, \_SB_.PCI0.PCIB.MIN1.MPMS) \_SB_.PCI0.LPCB.PHSS(0x84) } If(LEqual(Arg0, 0x3)) { Store(0x0, \_SB_.PCI0.USB0.U0EN) Store(0x0, \_SB_.PCI0.USB1.U1EN) Store(0x0, \_SB_.PCI0.USB2.U2EN) Store(0x1, \_SB_.PCI0.LPCB.RIEN) Store(\_SB_.PCI0.LPCB.RIS_, \_SB_.PCI0.LPCB.RIS_) Store(0x1, \_SB_.PCI0.LPCB.A97E) Store(\_SB_.PCI0.LPCB.A97S, \_SB_.PCI0.LPCB.A97S) Store(0x1, \_SB_.PCI0.PCIB.MIN1.MPME) Store(\_SB_.PCI0.PCIB.MIN1.MPMS, \_SB_.PCI0.PCIB.MIN1.MPMS) If(LEqual(OSTP, 0x0)) { // Unknown OS \_SB_.PCI0.LPCB.PHSS(0x80) } Else { \_SB_.PCI0.LPCB.PHSS(0x86) } } If(LEqual(Arg0, 0x4)) { If(LGreater(OSTP, 0x0)) { // Some known OS \_SB_.PCI0.LPCB.PHSS(0xe) } } If(LEqual(OSTP, 0x0)) { // Unknown OS \_SB_.PCI0.LPCB.S3SV() } } // _WAK - System Wake // // After the system wakes from a sleeping state, it // will invoke the \_WAK method. This operation // occurs asynchronously with other driver // notifications in the system and is not the first // action to be taken when the system wakes. The // ACPI system firmware for _WAK issues device, // thermal, and other notifications to ensure that // OSPM checks the state of devices, thermal zones, // and so on, that could not be maintained during // the system sleeping state. Hardware is not // obligated to track the state needed to supply the // resulting status; however, this method can return // status concerning the last sleep operation // initiated by OSPM. The result codes can be used // to provide additional information to OSPM or // user. // // IN: Arg0 SleepState. 1=S1,2=S2,3=S3,4=S4,5=S5 // OUT: Package Result of wake: // Entry Type Description // ------------------------------------- // // 0 Integer [0] 1 = Wake signalled // but failed due to lack // of power // [1] 1 = Wake signalled // but failed due to // thermal condition. // 1 Integer Actual sleep state // entered. 0 = Don't // know // Method(_WAK, 1) { If(LEqual(Arg0, 0x3)) { If(LEqual(OSTP, 0x3)) { // Windows XP If(LEqual(\_SB_.PCI0.LPCB.EC0_.ECOK, 0x1)) { Store(0x0, \_SB_.PCI0.LPCB.EC0_.RSMA) Store(\_SB_.PCI0.LPCB.EC0_.RSMT, Local0) Multiply(Local0, 0x68, Local0) Divide(Local0, 0x64, , Local0) Store(Local0, WAKT) } } Else { Store(0x1, ECDY) } If(LEqual(OSTP, 0x0)) { // Unknown OS \_SB_.PCI0.LPCB.S3RS() } \_SB_.PCI0.LPCB.PHSS(0x81) } If(LEqual(Arg0, 0x1)) { Or(\_SB_.PCI0.LPCB.SIRQ, 0x80, /* **** opcode has no effect */) \_SB_.PCI0.LPCB.PHSS(0x85) } If(LEqual(Arg0, 0x4)) { // Notify 0x02 - Device Wake. Device woke up self/system Notify(\_SB_.PWRB, 0x2) If(LGreater(OSTP, 0x0)) { // Known OS \_SB_.PCI0.LPCB.PHSS(0xf) } Else { \_SB_.PCI0.LPCB.S3RS() } } If(LEqual(\_SB_.PCI0.LPCB.EC0_.ECOK, 0x1)) { Store(\_SB_.PCI0.LPCB.EC0_.CSPR, Local1) If(LEqual(Local1, DCKF)) { Store(0x0, \_SB_.PCI0.LPCB.COMA.SRSM) } Else { If(Local1) { Store(0x0, \_SB_.PCI0.LPCB.COMA.SRSM) } Else { // Notify 0x00 - Bus Check. Check device and all children Notify(\_SB_.PCI0.LPCB.COMA, 0x0) } If(LEqual(Arg0, 0x4)) { Store(0x1, \_SB_.PCI0.LPCB.EC0_.FSPR) } } } Return(Package(0x02){0x00, 0x00}) } Scope(_GPE) { Method(_L03) { // Notify 0x02 - Device Wake. Device woke up self/system Notify(\_SB_.PCI0.USB0, 0x2) } Method(_L04) { // Notify 0x02 - Device Wake. Device woke up self/system Notify(\_SB_.PCI0.USB1, 0x2) } Method(_L08) { // Notify 0x02 - Device Wake. Device woke up self/system Notify(\_SB_.PCI0.PCIB, 0x2) } Method(_L0B) { // Notify 0x02 - Device Wake. Device woke up self/system Notify(\_SB_.PCI0.PCIB, 0x2) } Method(_L0C) { // Notify 0x02 - Device Wake. Device woke up self/system Notify(\_SB_.PCI0.USB2, 0x2) } Method(_L1D) { // LCD Lid open/close Store("=====GPE_L1D=====", Debug) Not(\_SB_.PCI0.LPCB.LPOL, \_SB_.PCI0.LPCB.LPOL) // Notify 0x80 - Lid Status Changed (Opened/Closed) Notify(\_SB_.LID_, 0x80) /* If(\_SB_.PCI0.LPCB.LPOL) { // LCD open Notify(\_SB_.LID_, 0x80) } Else { // LCD close Notify(\_SB_.LID_, 0x80) } */ } } Scope(_SB_) { Device(LID_) { // _HID - Hardware ID // // Supplies OSPM with the device's Plug and Play // hardware ID. When describing a platform, use of // any _HID objects is optional. However, a _HID // object must be used to describe any device that // will be enumerated by OSPM. OSPM only enumerates // a device when no bus enumerator can detect the // device ID. For example, devices on an ISA bus are // enumerated by OSPM. Use the _ADR object to // describe devices enumerated by bus enumerators // other than OSPM. // Name(_HID,EISAID("PNP0C0D") /* 0x0d0cd041 */) // _LID - System Lid Status // // The current status of the lid. // // IN: None // OUT: LidStatus 0 = Closed, 1 = Open // Method(_LID) { Return(\_SB_.PCI0.LPCB.LPOL) } } // // PWRB - Control-Method Power Button // Device(PWRB) { Name(_HID,EISAID("PNP0C0C") /*0x0c0cd041*/) } // // SLPB - Control-Method Sleep Button // Device(SLPB) { Name(_HID,EISAID("PNP0C0E") /*0x0e0cd041*/) } // // PCI0 - PCI Host Bridge // Device(PCI0) { Name(_HID,EISAID("PNP0A03") /*0x030ad041*/) // _BBN - Base Bus Number // // For multi-root PCI machines, _BBN evaluates to the // the PCI bus number that the BIOS assigns. This is // needed to access a PCI_Config operation region // for the specific bus. The _BBN object must be // unique for every host bridge within a segment // since it is the PCI bus number. // Name(_BBN, 0x0) // _ADR - Device Address // // Supplies OSPM with the address of a device on its // parent bus. An _ADR object must be used to // specify the address of any device on a bus that // has a standard enumeration algorithm. // An _ADR object can be used to provide capabilities // to the specified address even if a device is not // present. This allows the system to provide // capabilities to a slot on the parent bus. // OSPM infers the parent bus from the location of // the _ADR object's device package in the ACPI // namespace. _ADR object information must be static // and can be defined for the following bus types: // // Bus Address Encoding // EISA EISA slot number 0-F // Floppy Drive select values used for // programming the floppy // controller to access the // specified INT13 unit number. The // _ADRs should be sorted based on // drive select encoding from 0-3. // // IDE Controller 0 - Primary Channel,1 - Secondary // Channel // IDE Channel 0 - Master drive, 1 - Slave drive // // PCI High word - Device #, Low word - // Function #. (for example, device // 3, function 2 is 0x00030002). // // PCMCIA Socket #; 0 - First Socket // PC CARD Socket #; 0 - First Socket // SMBus Lowest Slave Address // USB Root HUB Only one child of the host // controller. It must have an _ADR // of 0. No other children or // values of _ADR are allowed. // USB Ports Port number Name(_ADR, 0x0) // _INI - Device Initialization // // Performs device specific initialization. Located // under a device object and is run only when OSPM // loads a description table. There are restrictions // related to when this method is called and // governing writing code for this method. The _INI // method must only access Operation Regions that // have been indicated to available as defined by // the _REG method. Run before _ADR, _CID, _HID, // _SUN, and _UID are run. If the _STA method // indicates that the device is present, OSPM will // evaluate the _INI for the device (if the _INI // method exists) and will examine each of the // children of the device for _INI methods. If the // _STA method indicates that the device is not // present, OSPM will not run the _INI and will not // examine the children of the device for _INI // methods. If the device becomes present after the // table has already been loaded, OSPM will not // evaluate the _INI method, nor examine the // children for _INI methods. // The _INI control method is generally used to // switch devices out of a legacy operating mode. // For example, BIOSes often configure CardBus // controllers in a legacy mode to support legacy // operating systems. Before enumerating the device // with an ACPI operating system, the CardBus // controllers must be initialized to CardBus mode. // For such systems, the vendor can include an _INI // control method under the CardBus controller to // switch the device into CardBus mode. // // IN: None // OUT: None Method(_INI) { // If(CondRefOf(_OS_, Local0)) { // If(LEqual(_OS_,"Windows 2001")) { // Store(0x3, OSTP) // } // Else { // Store(0x4, OSTP) // } // } External(\_OSI) // Name(\_OSI, 0x1) If(CondRefOf(_OSI, Local0)) { // If(\_OSI("Windows 2001")) { If(\_OSI) { // "Windows 2001" Store(0x3, OSTP) // "Windows 2001" = Windows XP Store("Windows XP detected", Debug) } Else { Store(0x4, OSTP) // Unknown OSI capable OS Store("Unsupported OSI capable OS detected", Debug) } } Else { If(LEqual(SizeOf(_OS_), 0x14)) { Store(0x2, OSTP) // "Microsoft Windows NT" Store("Microsoft Windows NT detected", Debug) } Else { If(LEqual(SizeOf(_OS_), 0x27)) { Store(0x1, OSTP) // "Microsoft WindowsME: Millennium Edition" Store("Microsoft WindowsME: Millennium Edition detected", Debug) } Else { Store(0x0, OSTP) // ??? Unknown Store("Unknown OS detected", Debug) } } } Store("Detected _OS_:", Debug) Store(\_OS_, Debug) Store(OSTP, OSYS) Store(0x0, \_SB_.PCI0.LPCB.CMAD) } OperationRegion(HBUS, PCI_Config, 0x40, 0xc0) Field(HBUS, DWordAcc, NoLock, Preserve) { Offset(0x12), , 3, IGDE, 1, Offset(0x18), , 7, HENA, 1, , 4, PM0H, 2, Offset(0x1a), PM1L, 2, , 2, PM1H, 2, Offset(0x1b), PM2L, 2, , 2, PM2H, 2, Offset(0x1c), PM3L, 2, , 2, PM3H, 2, Offset(0x1d), PM4L, 2, , 2, PM4H, 2, Offset(0x1e), PM5L, 2, , 2, PM5H, 2, Offset(0x1f), PM6L, 2, , 2, PM6H, 2, Offset(0x20), DRB0, 8, DRB1, 8, DRB2, 8, DRB3, 8, DRB4, 8, DRB5, 8, DRB6, 8, DRB7, 8, Offset(0x30), DRA0, 3, , 1, DRA1, 3, Offset(0x31), DRA2, 3, , 1, DRA3, 3, Offset(0x32), DRA4, 3, , 1, DRA5, 3, Offset(0x33), DRA6, 3, , 1, DRA7, 3, Offset(0x34) } Name(BUF0, Buffer(0x0201) {0x88, 0xe, 0x0, 0x2, 0xc, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x87, 0x18, 0x0, 0x1, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf7, 0xc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf8, 0xc, 0x0, 0x0, 0x0, 0x47, 0x1, 0xf8, 0xc, 0xf8, 0xc, 0x1, 0x8, 0x87, 0x18, 0x0, 0x1, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf3, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x0, 0xff, 0xff, 0xb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc, 0x0, 0xff, 0x3f, 0xc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0xc, 0x0, 0xff, 0x7f, 0xc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80, 0xc, 0x0, 0xff, 0xbf, 0xc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0, 0xc, 0x0, 0xff, 0xff, 0xc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd, 0x0, 0xff, 0x3f, 0xd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0xd, 0x0, 0xff, 0x7f, 0xd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80, 0xd, 0x0, 0xff, 0xbf, 0xd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0, 0xd, 0x0, 0xff, 0xff, 0xd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe, 0x0, 0xff, 0x3f, 0xe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0xe, 0x0, 0xff, 0x7f, 0xe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80, 0xe, 0x0, 0xff, 0xbf, 0xe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0, 0xe, 0x0, 0xff, 0xff, 0xe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x0, 0xff, 0xff, 0xf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0xff, 0xbf, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x87, 0x18, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x79, 0x0 }) // _CRS - Current Resource Settings // // Evaluates to a buffer describing the resources // currently allocated to a device. Additionally, a // bus device must supply the resources that it // decodes and can assign to child devices. If a // device is disabled, then _CRS returns a valid // resource template for the device, but the actual // resource assignments in the return byte stream // are ignored. If the device is disabled when _CRS // is called, it must remain disabled. // // IN: None // OUT: Buffer Resource descriptor Method(_CRS, 0, Serialized) { If(PM1L) { CreateDWordField(BUF0, 0x80, C0LN) Store(Zero, C0LN) } If(LEqual(PM1L, 0x1)) { CreateBitField(BUF0, 0x0378, C0RW) Store(Zero, C0RW) } If(PM1H) { CreateDWordField(BUF0, 0x9b, C4LN) Store(Zero, C4LN) } If(LEqual(PM1H, 0x1)) { CreateBitField(BUF0, 0x0450, C4RW) Store(Zero, C4RW) } If(PM2L) { CreateDWordField(BUF0, 0xb6, C8LN) Store(Zero, C8LN) } If(LEqual(PM2L, 0x1)) { CreateBitField(BUF0, 0x0528, C8RW) Store(Zero, C8RW) } If(PM2H) { CreateDWordField(BUF0, 0xd1, CCLN) Store(Zero, CCLN) } If(LEqual(PM2H, 0x1)) { CreateBitField(BUF0, 0x0600, CCRW) Store(Zero, CCRW) } If(PM3L) { CreateDWordField(BUF0, 0xec, D0LN) Store(Zero, D0LN) } If(LEqual(PM3L, 0x1)) { CreateBitField(BUF0, 0x06d8, D0RW) Store(Zero, D0RW) } If(PM3H) { CreateDWordField(BUF0, 0x0107, D4LN) Store(Zero, D4LN) } If(LEqual(PM3H, 0x1)) { CreateBitField(BUF0, 0x07b0, D4RW) Store(Zero, D4RW) } If(PM4L) { CreateDWordField(BUF0, 0x0122, D8LN) Store(Zero, D8LN) } If(LEqual(PM4L, 0x1)) { CreateBitField(BUF0, 0x0888, D8RW) Store(Zero, D8RW) } If(PM4H) { CreateDWordField(BUF0, 0x013d, DCLN) Store(Zero, DCLN) } If(LEqual(PM4H, 0x1)) { CreateBitField(BUF0, 0x0960, DCRW) Store(Zero, DCRW) } If(PM5L) { CreateDWordField(BUF0, 0x0158, E0LN) Store(Zero, E0LN) } If(LEqual(PM5L, 0x1)) { CreateBitField(BUF0, 0x0a38, E0RW) Store(Zero, E0RW) } If(PM5H) { CreateDWordField(BUF0, 0x0173, E4LN) Store(Zero, E4LN) } If(LEqual(PM5H, 0x1)) { CreateBitField(BUF0, 0x0b10, E4RW) Store(Zero, E4RW) } If(PM6L) { CreateDWordField(BUF0, 0x018e, E8LN) Store(Zero, E8LN) } If(LEqual(PM6L, 0x1)) { CreateBitField(BUF0, 0x0be8, E8RW) Store(Zero, E8RW) } If(PM6H) { CreateDWordField(BUF0, 0x01a9, ECLN) Store(Zero, ECLN) } If(LEqual(PM6H, 0x1)) { CreateBitField(BUF0, 0x0cc0, ECRW) Store(Zero, ECRW) } If(PM0H) { CreateDWordField(BUF0, 0x01c4, F0LN) Store(Zero, F0LN) } If(LEqual(PM0H, 0x1)) { CreateBitField(BUF0, 0x0d98, F0RW) Store(Zero, F0RW) } CreateDWordField(BUF0, 0x01d3, M1MN) CreateDWordField(BUF0, 0x01d7, M1MX) CreateDWordField(BUF0, 0x01df, M1LN) Multiply(0x02000000, DRB5, M1MN) Add(Subtract(M1MX, M1MN, ), 0x1, M1LN) ShiftRight(And(\_SB_.PCI0.LPCB.MTSE, 0x00038000, ), 0xf, Local0) If(And(Local0, 0x4, )) { CreateDWordField(BUF0, 0x01ee, M2MN) CreateDWordField(BUF0, 0x01f2, M2MX) CreateDWordField(BUF0, 0x01fa, M2LN) Store(0xfed00000, M2MN) Store(0xfed003ff, M2MX) Store(0x0400, M2LN) If(LEqual(Local0, 0x5)) { Store(0xfed01000, M2MN) Store(0xfed013ff, M2MX) } If(LEqual(Local0, 0x6)) { Store(0xfed02000, M2MN) Store(0xfed023ff, M2MX) } If(LEqual(Local0, 0x7)) { Store(0xfed03000, M2MN) Store(0xfed033ff, M2MX) } } Return(BUF0) } // _PRT - PCI Routing Table // // PCI interrupts are inherently non-hierarchical. // PCI interrupt pins are wired to interrupt inputs // of the interrupt controllers. _PRT provides a // mapping from PCI interrupt pins to the interrupt // inputs of the interrupt controllers. _PRT is // required under all PCI root bridges. _PRT // evaluates to a package containing an array of // packages, each of which describes the mapping of // a PCI interrupt pin. Note: The function number in // the _PRT packages must be FFFF, that is, any // function number. The format of each package is: // // Entry Type Description // ---------------------------------------- // 0 Integer Address of the device // 1 Integer PCI pin number of the device // (0=INTA#, 1=INTB#, 2=INTC#, // 3=INTD#) // 2 Name Name of the device which the pin is // connected or 0 if the global pool // // 3 Integer Index of the interrupt in the // specified device // Name(_PRT, Package(0x7) { Package(0x4) { 0x0002ffff, 0x0, \_SB_.PCI0.LPCB.LNKA, 0x0, }, Package(0x4) { 0x0002ffff, 0x1, \_SB_.PCI0.LPCB.LNKB, 0x0, }, Package(0x4) { 0x001dffff, 0x0, \_SB_.PCI0.LPCB.LNKA, 0x0, }, Package(0x4) { 0x001dffff, 0x1, \_SB_.PCI0.LPCB.LNKD, 0x0, }, Package(0x4) { 0x001dffff, 0x2, \_SB_.PCI0.LPCB.LNKC, 0x0, }, Package(0x4) { 0x001fffff, 0x0, \_SB_.PCI0.LPCB.LNKC, 0x0, }, Package(0x4) { 0x001fffff, 0x1, \_SB_.PCI0.LPCB.LNKB, 0x0, }, }) Name(\DSEN, 0x1) Device(GRFX) { // _ADR - Device Address // // Supplies OSPM with the address of a device on its // parent bus. An _ADR object must be used to // specify the address of any device on a bus that // has a standard enumeration algorithm. // An _ADR object can be used to provide capabilities // to the specified address even if a device is not // present. This allows the system to provide // capabilities to a slot on the parent bus. // OSPM infers the parent bus from the location of // the _ADR object's device package in the ACPI // namespace. _ADR object information must be static // and can be defined for the following bus types: // // Bus Address Encoding // EISA EISA slot number 0-F // Floppy Drive select values used for // programming the floppy // controller to access the // specified INT13 unit number. The // _ADRs should be sorted based on // drive select encoding from 0-3. // // IDE Controller 0 - Primary Channel,1 - Secondary // Channel // IDE Channel 0 - Master drive, 1 - Slave drive // // PCI High word - Device #, Low word - // Function #. (for example, device // 3, function 2 is 0x00030002). // // PCMCIA Socket #; 0 - First Socket // PC CARD Socket #; 0 - First Socket // SMBus Lowest Slave Address // USB Root HUB Only one child of the host // controller. It must have an _ADR // of 0. No other children or // values of _ADR are allowed. // USB Ports Port number Name(_ADR, 0x00020000) // _PSC - Power Set Current // // Evaluates to the current device state. Not // required if the device state can be inferred by // the Power Resource settings. This would be the // case when the device does not require a _PS0, // _PS1, _PS2, or _PS3 control method. // Name(_PSC, 0x0) Name(VRSM, 0x0) // _PS0 - Power Set to D0 // // Puts the specific device into its D0 state. Can // only access Operation Regions that are either // always available while in a system working state // or that are available when the Power Resources // referenced by the _PR0 object are all ON. // // IN: None // OUT: None // Method(_PS0) { If(LAnd(_PSC, VRSM)) { Store(0x0, VRSM) } Store(0x0, _PSC) } Method(_PS3) { Store(0x1, VRSM) Store(0x3, _PSC) } Name(CADL, 0x1) Name(CSTE, 0x1) Name(NSTE, 0x1) // _DOS - Display Output Switching // // Many ACPI machines currently reprogram the active // display output automatically when the user // presses the display toggle switch on the // keyboard. This is done because most video device // drivers are currently not capable of being // notified synchronously of such state changes. // However, this behavior violates the ACPI // specification, because the system modifies some // graphics device registers. // // The existence of the _DOS method indicates that // the system BIOS is capable of automatically // switching the active display output or // controlling the brightness of the LCD. If it // exists at all, the _DOS method must be present // for all display output devices. This method is // required if the system supports display switching // or LCD brightness control. // // The _DOS method controls this automatic switching // behavior. This method should do so by saving the // parameter passed to this method in a global // variable somewhere in the BIOS data segment. The // system BIOS then checks the value of this // variable when doing display switching. This // method is also used to control the generation of // the display switching Notify(VGA, 0x80/0x81). The // system BIOS, when doing switching of the active // display, must verify the state of the variable // set by the _DOS method. The default value of this // variable must be 1. // // IN: Arg0 VideoBiosControl. [1:0] 0: The system BIOS should not // automatically switch (toggle) the // active display output, but // instead just save the desired // state change for the display // output devices in variables // associated with each display // output, and generate the display // switch event. OSPM can query // these state changes by calling // the _DGS method. // . 1: The system BIOS should // automatically switch (toggle) // the active display output, // with no interaction required // on the OS part. The display // switch event should not be // generated in this case. // . 2: The _DGS values should be // locked. It's highly recommended // that the system BIOS do nothing // when hotkey pressed. No switch, // no notification. // . 3: Reserved // [2] 0: The system BIOS should // automatically control the // brightness level of the LCD when // the power changes from AC to DC. // // . 1: The system BIOS should not // automatically control the // brightness level of the LCD when // the power changes from AC to DC. // // OUT: None Method(_DOS, 1) { Store(And(Arg0, 0x3, ), DSEN) } // _DOD - Display Output Devices // // Enumerates devices attached to the display // adapter. Required if integrated controller // supports output switching. On many laptops today, // a number of devices can be connected to the // graphics adapter in the machine. These devices // are on the motherboard and generally are not // directly enumerable by the video driver; for this // reason, all motherboard VGA attached devices are // listed in the ACPI namespace. // // These devices fall into two categories: // // o Video output devices. For example, a machine // with a single display device on the motherboard // can have three possible output devices attached // to it, such as a TV, a CRT, or a panel. // o Non-video output devices. For example, TV Tuner, // DVD decoder, Video Capture. They just attach to // VGA and their power management closely relates // to VGA. // // Both ACPI and the video driver have the ability to // program and configure output devices. This means // that both ACPI and the video driver must // enumerate the devices using the same IDs. Because // there are no standard configurations for display // output devices, no standard ID generation // mechanism can be used. To solve this problem, // _DOD evaluates to a list of devices attached to // the graphics adapter, along with device-specific // configuration information. This information will // allow the cooperation between ACPI components and // the video driver. // // Every child device enumerated in the ACPI // namespace under the graphics adapter must be // specified in this list of devices. // // IN: None // OUT: VideoDevicePackage Each package element is an // Integer with this // definition: // // [15:0] Device ID. The // device ID must // match the IDs // specified by // Video Chip // Vendors. They // must also be // unique under // VGA namespace. // Common IDs // include: // 0x0100 = // Monitor, // 0x0200 = // Panel, 0x0300 // = TV,0x0000 = // Other // [16] BIOS. Can // detect the // device. // [17] Non-VGA output // device whose // power is // related to the // VGA device. // This can be // used when // specifying // devices like // TV Tuner, DVD // decoder, Video // Capture, and // so on. // [20:18] For VGA // multiple-head // devices, this // specifies head // ID. // [31:21] Reserved. Must // be 0 Method(_DOD) { \_SB_.PCI0.LPCB.PHSS(0x76) Store(\_SB_.PCI0.LPCB.INF_, CADL) Name(PSIZ, 0x0) Store(CADL, Local0) While(Local0) { If(And(Local0, 0x1, )) { Increment(PSIZ) } ShiftRight(Local0, 0x1, Local0) } If(LEqual(PSIZ, 0x1)) { Return(Package(0x1) { 0x00010400, }) } If(LEqual(PSIZ, 0x2)) { Name(PPTR, 0x1) Name(VID2, Package(0x2) { 0x00010400, 0x00010100, }) If(And(CADL, 0x1, )) { Store(0x00010100, Index(VID2, PPTR, )) } If(And(CADL, 0x2, )) { Store(0x00010200, Index(VID2, PPTR, )) } Return(VID2) } If(LEqual(PSIZ, 0x3)) { Return(Package(0x3) { 0x00010400, 0x00010100, 0x00010200, }) } Return(Zero) } Device(LFP_) { Name(_ADR, 0x0400) // _DCS - Device Status // // Required if hotkey display switching is // supported. // // IN: None // OUT: DeviceStatus [0] 1 = Output connector exists // in the system now // [1] 1 = Output is activated // // [2] 1 = Output is ready to // switch // [3] 1 = Output is functioning // properly // [4] 1 = Device is attached // // [31:5] Reserved. // Method(_DCS) { \_SB_.PCI0.LPCB.PHSS(0x75) Store(\_SB_.PCI0.LPCB.INF_, CSTE) If(And(CSTE, 0x8, )) { Return(0x1f) } Return(0x1d) } // _DGS - Device Get State // // Query the state (active or inactive) of the output // device. Required if hotkey display switching is // supported. // // IN: None // OUT: NextDesiredState [0] 0 = Next desired // state is inactive // . 1 = Next desired // state is active. // Method(_DGS) { If(And(NSTE, 0x8, )) { Return(0x1) } Return(0x0) } // _DSS - Device Set State // // OSPM will call this method when it determines the // outputs can be activated or deactivated. OSPM // will manage this to avoid flickering as much as // possible. This method is required if hotkey // display switching is supported. // // IN: Arg0 DeviceState. [0] 0 = Set device inactive // . 1 = Set device active // [30] 1 = Ignore bit 31 // 0 = Don't do actual switching, // but change _DGS to next // state[31] 0 = Don't do actual // switching, just cache the // change 1 = Do actual // switch // OUT: None Method(_DSS, 1) { } } Device(CRT_) { Name(_ADR, 0x0100) Method(_DCS) { \_SB_.PCI0.LPCB.PHSS(0x75) Store(\_SB_.PCI0.LPCB.INF_, CSTE) If(And(CSTE, 0x1, )) { Return(0x1f) } Return(0x1d) } Method(_DGS) { If(And(NSTE, 0x1, )) { Return(0x1) } Return(0x0) } Method(_DSS, 1) { } } Device(DTV_) { Name(_ADR, 0x0200) Method(_DCS) { \_SB_.PCI0.LPCB.PHSS(0x75) Store(\_SB_.PCI0.LPCB.INF_, CSTE) If(And(CSTE, 0x2, )) { Return(0x1f) } Return(0x1d) } Method(_DGS) { If(And(NSTE, 0x2, )) { Return(0x1) } Return(0x0) } Method(_DSS, 1) { } } Method(DSSW) { If(LEqual(0x0, DSEN)) { \_SB_.PCI0.LPCB.PHSS(0x76) If(LNot(LEqual(\_SB_.PCI0.LPCB.INF_, CADL))) { Store(\_SB_.PCI0.LPCB.INF_, CADL) Notify(\_SB_.PCI0, 0x0) Sleep(0x03e8) } \_SB_.PCI0.LPCB.PHSS(0x77) Store(\_SB_.PCI0.LPCB.INF_, NSTE) // Notify 0x80 - // **** unknown object notifiation value Notify(\_SB_.PCI0.GRFX, 0x80) } If(LEqual(0x1, DSEN)) { \_SB_.PCI0.LPCB.PHSS(0x1) // Notify 0x81 - // **** unknown object notifiation value Notify(\_SB_.PCI0.GRFX, 0x81) } } } // // FIGD - Motherboard Resources // Device(FIGD) { Name(_HID,EISAID("PNP0C02") /*0x020cd041*/) // _UID - Unique ID // // Provides OSPM with a serial number-style ID of a // device (or battery), which does not change across // reboots. This object is optional, but is required // when the device has no other way to report a // persistent unique device ID. When a system has // two devices that report the same _HID, each // device must have a _UID object. When reported, // the UID needs to be unique only among devices // with the same device ID. OSPM typically uses the // unique device ID to ensure that the device // -specific information, such as network protocol // binding information, is remembered for the device // even if its relative location changes. For most // integrated devices, this object contains a unique // identifier. For other devices, like a docking // station, this object can be a control method that // returns the unique docking station ID. A _UID // object evaluates to either a numeric value or a // string. Name(_UID, 0x1) // _STA - Device Status // // Evaluates to the status of a device,which can be // one of the following: enabled, disabled, or // removed. If the device is not present (bit 0 = 0) // then the device must not decode hardware // resources (bit 1 = 0). A device can only decode // its hardware resources if both present and // enabled (bits 0,1 = 1). If the device is not // present (bit 0 = 0) or not enabled (bit 1 = 1), // then the device must not decode its resources. // If a device is present in the machine, but should // not be displayed in OSPM user interface, bit 2 is // 0. For example, a notebook could have joystick // hardware (thus it is present and decoding its // resources), but the connector for plugging in the // joystick requires a port replicator. If the port // replicator is not plugged in, the joystick should // not appear in the UI, so bit 2 is 0. // If a device object does not have an _STA object, // then OSPM assumes that all of the device is is // present, enabled, shown in the UI, and // functioning). // Must not reference any operation regions that have // not been declared available by a _REG method. // // IN: None // OUT: Integer [0] 1 = Device is present. 0 = Device // not present // [1] 1 = Device decodes resources. 0 = // Device doesn't decode resources // // [2] 1 = Device shown in GUI. 0 = // Device not shown in GUI // [3] 1 = Device is functioning OK. 0 = // Device is not functioning // [4] 1 = Battery present. 0 = Battery // not present Method(_STA) { If(LEqual(\_SB_.PCI0.LPCB.RVID, 0x1)) { If(LNot(LLess(OSTP, 0x2))) { // NT or XP or OSI capable??? OS If(LEqual(IGDE, 0x0)) { Return(0xb) } } } Return(0x0) } // _CRS - Current Resource Settings // // Evaluates to a buffer describing the resources // currently allocated to a device. Additionally, a // bus device must supply the resources that it // decodes and can assign to child devices. If a // device is disabled, then _CRS returns a valid // resource template for the device, but the actual // resource assignments in the return byte stream // are ignored. If the device is disabled when _CRS // is called, it must remain disabled. // Name(_CRS, Buffer(0x03f2) {0x47, 0x1, 0xb0, 0x7, 0xb0, 0x7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x7, 0xc0, 0x7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xb, 0xb0, 0xb, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xb, 0xc0, 0xb, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xf, 0xb0, 0xf, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xf, 0xc0, 0xf, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x13, 0xb0, 0x13, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x13, 0xc0, 0x13, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x17, 0xb0, 0x17, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x17, 0xc0, 0x17, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x1b, 0xb0, 0x1b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x1b, 0xc0, 0x1b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x1f, 0xb0, 0x1f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x1f, 0xc0, 0x1f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x23, 0xb0, 0x23, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x23, 0xc0, 0x23, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x27, 0xb0, 0x27, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x27, 0xc0, 0x27, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x2b, 0xb0, 0x2b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x2b, 0xc0, 0x2b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x2f, 0xb0, 0x2f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x2f, 0xc0, 0x2f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x33, 0xb0, 0x33, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x33, 0xc0, 0x33, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x37, 0xb0, 0x37, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x37, 0xc0, 0x37, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x3b, 0xb0, 0x3b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x3b, 0xc0, 0x3b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x3f, 0xb0, 0x3f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x3f, 0xc0, 0x3f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x43, 0xb0, 0x43, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x43, 0xc0, 0x43, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x47, 0xb0, 0x47, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x47, 0xc0, 0x47, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x4b, 0xb0, 0x4b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x4b, 0xc0, 0x4b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x4f, 0xb0, 0x4f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x4f, 0xc0, 0x4f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x53, 0xb0, 0x53, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x53, 0xc0, 0x53, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x57, 0xb0, 0x57, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x57, 0xc0, 0x57, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x5b, 0xb0, 0x5b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x5b, 0xc0, 0x5b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x5f, 0xb0, 0x5f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x5f, 0xc0, 0x5f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x63, 0xb0, 0x63, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x63, 0xc0, 0x63, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x67, 0xb0, 0x67, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x67, 0xc0, 0x67, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x6b, 0xb0, 0x6b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x6b, 0xc0, 0x6b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x6f, 0xb0, 0x6f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x6f, 0xc0, 0x6f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x73, 0xb0, 0x73, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x73, 0xc0, 0x73, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x77, 0xb0, 0x77, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x77, 0xc0, 0x77, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x7b, 0xb0, 0x7b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x7b, 0xc0, 0x7b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x7f, 0xb0, 0x7f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x7f, 0xc0, 0x7f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x83, 0xb0, 0x83, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x83, 0xc0, 0x83, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x87, 0xb0, 0x87, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x87, 0xc0, 0x87, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x8b, 0xb0, 0x8b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x8b, 0xc0, 0x8b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x8f, 0xb0, 0x8f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x8f, 0xc0, 0x8f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x93, 0xb0, 0x93, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x93, 0xc0, 0x93, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x97, 0xb0, 0x97, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x97, 0xc0, 0x97, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x9b, 0xb0, 0x9b, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x9b, 0xc0, 0x9b, 0x1, 0x20, 0x47, 0x1, 0xb0, 0x9f, 0xb0, 0x9f, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x9f, 0xc0, 0x9f, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xa3, 0xb0, 0xa3, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xa3, 0xc0, 0xa3, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xa7, 0xb0, 0xa7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xa7, 0xc0, 0xa7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xab, 0xb0, 0xab, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xab, 0xc0, 0xab, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xaf, 0xb0, 0xaf, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xaf, 0xc0, 0xaf, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xb3, 0xb0, 0xb3, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xb3, 0xc0, 0xb3, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xb7, 0xb0, 0xb7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xb7, 0xc0, 0xb7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xbb, 0xb0, 0xbb, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xbb, 0xc0, 0xbb, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xbf, 0xb0, 0xbf, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xbf, 0xc0, 0xbf, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xc3, 0xb0, 0xc3, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xc3, 0xc0, 0xc3, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xc7, 0xb0, 0xc7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xc7, 0xc0, 0xc7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xcb, 0xb0, 0xcb, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xcb, 0xc0, 0xcb, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xcf, 0xb0, 0xcf, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xcf, 0xc0, 0xcf, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xd3, 0xb0, 0xd3, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xd3, 0xc0, 0xd3, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xd7, 0xb0, 0xd7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xd7, 0xc0, 0xd7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xdb, 0xb0, 0xdb, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xdb, 0xc0, 0xdb, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xdf, 0xb0, 0xdf, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xdf, 0xc0, 0xdf, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xe3, 0xb0, 0xe3, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xe3, 0xc0, 0xe3, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xe7, 0xb0, 0xe7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xe7, 0xc0, 0xe7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xeb, 0xb0, 0xeb, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xeb, 0xc0, 0xeb, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xef, 0xb0, 0xef, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xef, 0xc0, 0xef, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xf3, 0xb0, 0xf3, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xf3, 0xc0, 0xf3, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xf7, 0xb0, 0xf7, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xf7, 0xc0, 0xf7, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xfb, 0xb0, 0xfb, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xfb, 0xc0, 0xfb, 0x1, 0x20, 0x47, 0x1, 0xb0, 0xff, 0xb0, 0xff, 0x1, 0xc, 0x47, 0x1, 0xc0, 0xff, 0xc0, 0xff, 0x1, 0x20, 0x79, 0x0 }) } Device(PCIB) { Name(_ADR, 0x001e0000) Name(_PRT, Package(0x7) { Package(0x4) { 0xffff, 0x0, \_SB_.PCI0.LPCB.LNKA, 0x0, }, Package(0x4) { 0x0002ffff, 0x0, \_SB_.PCI0.LPCB.LNKC, 0x0, }, Package(0x4) { 0x0003ffff, 0x0, \_SB_.PCI0.LPCB.LNKD, 0x0, }, Package(0x4) { 0x0004ffff, 0x0, \_SB_.PCI0.LPCB.LNKA, 0x0, }, Package(0x4) { 0x0004ffff, 0x1, \_SB_.PCI0.LPCB.LNKB, 0x0, }, Package(0x4) { 0x0006ffff, 0x0, \_SB_.PCI0.LPCB.LNKD, 0x0, }, Package(0x4) { 0x0008ffff, 0x0, \_SB_.PCI0.LPCB.LNKE, 0x0, }, }) Device(ILAN) { Name(_ADR, 0x00080000) OperationRegion(IIDS, PCI_Config, 0x0, 0x4) Field(IIDS, DWordAcc, NoLock, Preserve) { ILID, 32 } Method(_STA) { If(LEqual(ILID, 0xffffffff)) { Return(0x0) } Else { Return(0xf) } } // _PRW - Power Resources for Wake // // Required for devices that have the ability to wake // the system from a system sleeping state. // Evaluates to a package of the following // definition: // // Entry Type Description // ---------------------------------------- // 0 Integer Event number in GPE block described // in the FADT used to enable the // wake event // . Package 0 = Name of GPE block device. 1 = // Event number in block // 1 Integer Lowest Sx state that can be entered // and still wake the system // 2+ Name Name of power resource which must // be ON in order to wake the system // // For OSPM to have the defined wake capability // properly enabled for the device, the following // must occur: // 1. All Power Resources referenced by elements 2 // through N are put into the ON state. // 2. If present, the _PSW method is executed to set // the device-specific registers to enable the // wake functionality of the device. // // Then, if the system wants to enter a sleeping // state: // 1. Interrupts are disabled. // 2. The sleeping state being entered must be // greater or equal to the power state declared // in element 1 of the _PRW object. // 3. The proper general-purpose register bits are // enabled. // // The system sleeping state specified must be a // state that the system supports (in other words, a // corresponding \_Sx object must exist in the // namespace). _PRW must evaluate to the same data // each time it is evaluated. All power resources // referenced must exist in the namespace. // Name(_PRW, Package(0x2) { 0xb, 0x4, }) } Device(CB1_) { Name(_ADR, 0x00040000) OperationRegion(CBD0, PCI_Config, 0x0, 0xc0) Field(CBD0, AnyAcc, NoLock, Preserve) { Offset(0x3c), CD3C, 8, Offset(0x44), CD44, 8 } Method(_INI) { Or(CD3C, 0xff, CD3C) Store(0x0, CD44) } } Device(CB2_) { Name(_ADR, 0x00040001) OperationRegion(CBD1, PCI_Config, 0x0, 0xc0) Field(CBD1, AnyAcc, NoLock, Preserve) { Offset(0x3c), CD3C, 8, Offset(0x44), CD44, 8 } Method(_INI) { Or(CD3C, 0xff, CD3C) Store(0x0, CD44) } } Device(MIN1) { Name(_ADR, 0x00020000) // _PSC - Power Set Current // // Evaluates to the current device state. Not // required if the device state can be inferred by // the Power Resource settings. This would be the // case when the device does not require a _PS0, // _PS1, _PS2, or _PS3 control method. // Name(_PSC, 0x0) OperationRegion(MIDS, PCI_Config, 0x0, 0xc8) Field(MIDS, DWordAcc, NoLock, Preserve) { MOID, 32, Offset(0xc4), Offset(0xc5), MPME, 1, , 6, MPMS, 1 } Method(_STA) { If(LEqual(MOID, 0xffffffff)) { Return(0x0) } Else { Return(0xf) } } Method(_PS0) { Store(0x0, _PSC) } Method(_PS1) { Store(0x1, _PSC) } Method(_PS2) { Store(0x2, _PSC) } Method(_PS3) { Store(0x3, _PSC) } Name(_PRW, Package(0x2) { 0x8, 0x3, }) } Device(MIN2) { Name(_ADR, 0x00060000) Name(_PSC, 0x0) OperationRegion(LNDS, PCI_Config, 0x0, 0x4) Field(LNDS, DWordAcc, NoLock, Preserve) { LNID, 32 } Method(_STA) { If(LEqual(LNID, 0xffffffff)) { Return(0x0) } Else { Return(0xf) } } Method(_PS0) { Store(0x0, _PSC) } Method(_PS1) { Store(0x1, _PSC) } Method(_PS2) { Store(0x2, _PSC) } Method(_PS3) { Store(0x3, _PSC) } Name(_PRW, Package(0x2) { 0xb, 0x4, }) } Device(TI94) { Name(_ADR, 0x0) Name(_PSC, 0x0) OperationRegion(TIDS, PCI_Config, 0x0, 0x4) Field(TIDS, DWordAcc, NoLock, Preserve) { TIID, 32 } Method(_STA) { If(LEqual(TIID, 0xffffffff)) { Return(0x0) } Else { Return(0xf) } } Method(_PS0) { Store(0x0, _PSC) } Method(_PS1) { Store(0x1, _PSC) } Method(_PS2) { Store(0x2, _PSC) } Method(_PS3) { Store(0x3, _PSC) } } } Device(LPCB) { Name(_ADR, 0x001f0000) OperationRegion(PMIO, SystemIO, 0x1000, 0x2c) Field(PMIO, WordAcc, Lock, Preserve) { AccessAs(WordAcc, 0), Offset(0x28), , 3, US1S, 1, US2S, 1, A97S, 1, Offset(0x29), RIS_, 1, , 2, PMES, 1, US3S, 1, Offset(0x2a), , 3, US1E, 1, US2E, 1, A97E, 1, Offset(0x2b), RIEN, 1, , 2, PMEE, 1, US3E, 1 } OperationRegion(GPIO, SystemIO, 0x1180, 0x3c) Field(GPIO, WordAcc, Lock, Preserve) { AccessAs(DWordAcc, 0), Offset(0xf), , 4, LV28, 1, Offset(0x2d), , 5, LPOL, 1, Offset(0x38), , 1, SRST, 1, Offset(0x39), , 2, ACPW, 1 } OperationRegion(LPCR, PCI_Config, 0x0, 0xff) Field(LPCR, ByteAcc, NoLock, Preserve) { Offset(0x8), RVID, 8, Offset(0x64), SIRQ, 8, Offset(0xe6), CMAD, 1 } OperationRegion(SMI0, SystemIO, 0x0000fe00, 0x00000002) Field(SMI0, AnyAcc, NoLock, Preserve) { SMIC, 8 } OperationRegion(SMI1, SystemMemory, 0x0f6ffead, 0x00000090) Field(SMI1, AnyAcc, NoLock, Preserve) { BCMD, 8, DID_, 32, INFO, 1024 } Field(SMI1, AnyAcc, NoLock, Preserve) { AccessAs(ByteAcc, 0), Offset(0x5), INF_, 8, INF1, 32 } Mutex(PSMX, 0) Method(PHSS, 1) { Acquire(PSMX, 0xffff) Store(0x80, BCMD) Store(Arg0, DID_) Store(Zero, SMIC) Release(PSMX) } OperationRegion(LPC0, PCI_Config, 0x40, 0xc0) Field(LPC0, AnyAcc, NoLock, Preserve) { Offset(0x20), PIRA, 8, PIRB, 8, PIRC, 8, PIRD, 8, Offset(0x28), PIRE, 8, PIRF, 8, PIRG, 8, PIRH, 8, Offset(0x90), MTSE, 32 } // // LNKA - PCI Interrupt Link // Device(LNKA) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x1) // _DIS - Disable Device // // Disables a device. While the device is disabled, // it must not be decoding any resources. Prior to // running this method, OSPM will have already put // the device in the D3 state. When a device is // disabled the _STA control method for this device // must return with the Disabled bit set. // // IN: None // OUT: None Method(_DIS, 0, Serialized) { Or(PIRA, 0x80, PIRA) } // _PRS - Possible Resource Settings // // Evaluates to a buffer that describes the possible // resource settings for the device. Specify a _PRS // for all the configurable devices. Static (non // -configurable) devices do not specify a _PRS // object. OSPM uses the information returned in // order to select a conflict-free resource // allocation without user intervention. Must not // reference any operation regions that have not // been declared available by a _REG method. // // The format of the data in a _PRS object follows // the same format as the _CRS object. If the device // is disabled when _PRS is called, it must remain // disabled. // Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) // _CRS - Current Resource Settings // // Evaluates to a buffer describing the resources // currently allocated to a device. Additionally, a // bus device must supply the resources that it // decodes and can assign to child devices. If a // device is disabled, then _CRS returns a valid // resource template for the device, but the actual // resource assignments in the return byte stream // are ignored. If the device is disabled when _CRS // is called, it must remain disabled. // // IN: None // OUT: Buffer Resource descriptor Method(_CRS, 0, Serialized) { Name(RTLA, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLA, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRA, 0x80, ))) { And(PIRA, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLA) } // _SRS - Set Resource Settings // // Takes one buffer argument that specifies new // resources for a device. The resource descriptors // in the byte stream argument must be specified in // the same order as listed in the _CRS byte stream. // A _CRS object can be used as a template to ensure // that the descriptors are in the correct format. // The settings must take effect before the _SRS // control method returns. Must not reference any // operation regions that have not been declared // available by a _REG method. If the device is // disabled, _SRS enables the device using the // specified resources. _SRS is not used to disable // a device; use the _DIS control method instead. // // IN: Arg0 Buffer. New device resource settings // OUT: None Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRA) } Method(_STA, 0, Serialized) { And(PIRA, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKB - PCI Interrupt Link // Device(LNKB) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x2) Method(_DIS) { Or(PIRB, 0x80, PIRB) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLB, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLB, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRB, 0x80, ))) { And(PIRB, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLB) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRB) } Method(_STA, 0, Serialized) { And(PIRB, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKC - PCI Interrupt Link // Device(LNKC) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x3) Method(_DIS) { Or(PIRC, 0x80, PIRC) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLC, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLC, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRC, 0x80, ))) { And(PIRC, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLC) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRC) } Method(_STA, 0, Serialized) { And(PIRC, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKD - PCI Interrupt Link // Device(LNKD) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x4) Method(_DIS) { Or(PIRD, 0x80, PIRD) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLD, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLD, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRD, 0x80, ))) { And(PIRD, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLD) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRD) } Method(_STA, 0, Serialized) { And(PIRD, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKE - PCI Interrupt Link // Device(LNKE) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x5) Method(_DIS) { Or(PIRE, 0x80, PIRE) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLE, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLE, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRE, 0x80, ))) { And(PIRE, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLE) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRE) } Method(_STA, 0, Serialized) { And(PIRE, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKF - PCI Interrupt Link // Device(LNKF) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x6) Method(_DIS) { Or(PIRF, 0x80, PIRF) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLF, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLF, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRF, 0x80, ))) { And(PIRF, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLF) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRF) } Method(_STA, 0, Serialized) { And(PIRF, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKG - PCI Interrupt Link // Device(LNKG) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x7) Method(_DIS) { Or(PIRG, 0x80, PIRG) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLG, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLG, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRG, 0x80, ))) { And(PIRG, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLG) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRF) } Method(_STA, 0, Serialized) { And(PIRG, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // LNKH - PCI Interrupt Link // Device(LNKH) { Name(_HID,EISAID("PNP0C0F") /*0x0f0cd041*/) Name(_UID, 0x8) Method(_DIS) { Or(PIRH, 0x80, PIRH) } Name(_PRS, Buffer(0x6) {0x23, 0xb8, 0xde, 0x18, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { Name(RTLH, Buffer(0x6) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 }) CreateWordField(RTLH, 0x1, IRQ0) Store(Zero, IRQ0) If(LNot(And(PIRH, 0x80, ))) { And(PIRH, 0xf, Local0) ShiftLeft(0x1, Local0, IRQ0) } Return(RTLH) } Method(_SRS, 1, Serialized) { CreateWordField(Arg0, 0x1, IRQ0) FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PIRH) } Method(_STA, 0, Serialized) { And(PIRH, 0x80, Local0) If(Local0) { Return(0x9) } Else { Return(0xb) } } } // // TIMR - PC Interval Timer // Device(TIMR) { Name(_HID,EISAID("PNP0100") /*0x0001d041*/) Name(BUF0, Buffer(0x12) {0x47, 0x1, 0x40, 0x0, 0x40, 0x0, 0x1, 0x4, 0x47, 0x1, 0x50, 0x0, 0x50, 0x0, 0x10, 0x4, 0x79, 0x0 }) Name(BUF1, Buffer(0x15) {0x47, 0x1, 0x40, 0x0, 0x40, 0x0, 0x1, 0x4, 0x47, 0x1, 0x50, 0x0, 0x50, 0x0, 0x10, 0x4, 0x22, 0x1, 0x0, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { If(And(MTSE, 0x00020000, )) { Return(BUF0) } Return(BUF1) } } // // IPIC - PC Interrupt Controller // Device(IPIC) { Name(_HID,EISAID("PNP0000") /*0xd041*/) Name(_CRS, Buffer(0x8d) {0x47, 0x1, 0x20, 0x0, 0x20, 0x0, 0x1, 0x2, 0x47, 0x1, 0x24, 0x0, 0x24, 0x0, 0x1, 0x2, 0x47, 0x1, 0x28, 0x0, 0x28, 0x0, 0x1, 0x2, 0x47, 0x1, 0x2c, 0x0, 0x2c, 0x0, 0x1, 0x2, 0x47, 0x1, 0x30, 0x0, 0x30, 0x0, 0x1, 0x2, 0x47, 0x1, 0x34, 0x0, 0x34, 0x0, 0x1, 0x2, 0x47, 0x1, 0x38, 0x0, 0x38, 0x0, 0x1, 0x2, 0x47, 0x1, 0x3c, 0x0, 0x3c, 0x0, 0x1, 0x2, 0x47, 0x1, 0xa0, 0x0, 0xa0, 0x0, 0x1, 0x2, 0x47, 0x1, 0xa4, 0x0, 0xa4, 0x0, 0x1, 0x2, 0x47, 0x1, 0xa8, 0x0, 0xa8, 0x0, 0x1, 0x2, 0x47, 0x1, 0xac, 0x0, 0xac, 0x0, 0x1, 0x2, 0x47, 0x1, 0xb0, 0x0, 0xb0, 0x0, 0x1, 0x2, 0x47, 0x1, 0xb4, 0x0, 0xb4, 0x0, 0x1, 0x2, 0x47, 0x1, 0xb8, 0x0, 0xb8, 0x0, 0x1, 0x2, 0x47, 0x1, 0xbc, 0x0, 0xbc, 0x0, 0x1, 0x2, 0x47, 0x1, 0xd0, 0x4, 0xd0, 0x4, 0x1, 0x2, 0x22, 0x4, 0x0, 0x79, 0x0 }) } // // RTC - PC Real-Time Clock // Device(RTC_) { Name(_HID,EISAID("PNP0B00") /*0x000bd041*/) Name(BUF0, Buffer(0xa) {0x47, 0x1, 0x70, 0x0, 0x70, 0x0, 0x1, 0x8, 0x79, 0x0 }) Name(BUF1, Buffer(0xd) {0x47, 0x1, 0x70, 0x0, 0x70, 0x0, 0x1, 0x8, 0x22, 0x0, 0x1, 0x79, 0x0 }) Method(_CRS, 0, Serialized) { If(And(MTSE, 0x00020000, )) { Return(BUF0) } Return(BUF1) } } // // MATH - Math Coprocessor // Device(MATH) { Name(_HID,EISAID("PNP0C04") /*0x040cd041*/) Name(_CRS, Buffer(0xd) {0x47, 0x1, 0xf0, 0x0, 0xf0, 0x0, 0x1, 0x1, 0x22, 0x0, 0x20, 0x79, 0x0 }) } // // DMAC - PC DMA Controller // Device(DMAC) { Name(_HID,EISAID("PNP0200") /*0x0002d041*/) Name(_CRS, Buffer(0x2d) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x20, 0x47, 0x1, 0x81, 0x0, 0x81, 0x0, 0x1, 0xf, 0x47, 0x1, 0x90, 0x0, 0x90, 0x0, 0x1, 0x2, 0x47, 0x1, 0x93, 0x0, 0x93, 0x0, 0x1, 0xd, 0x47, 0x1, 0xc0, 0x0, 0xc0, 0x0, 0x1, 0x20, 0x2a, 0x10, 0x1, 0x79, 0x0 }) } // // MBRD - Motherboard Resources // Device(MBRD) { Name(_HID,EISAID("PNP0C02") /*0x020cd041*/) Name(_CRS, Buffer(0x8a) {0x47, 0x1, 0x2e, 0x0, 0x2e, 0x0, 0x1, 0x2, 0x47, 0x1, 0x61, 0x0, 0x61, 0x0, 0x1, 0x1, 0x47, 0x1, 0x63, 0x0, 0x63, 0x0, 0x1, 0x1, 0x47, 0x1, 0x65, 0x0, 0x65, 0x0, 0x1, 0x1, 0x47, 0x1, 0x67, 0x0, 0x67, 0x0, 0x1, 0x1, 0x47, 0x1, 0x80, 0x0, 0x80, 0x0, 0x1, 0x1, 0x47, 0x1, 0x92, 0x0, 0x92, 0x0, 0x1, 0x1, 0x47, 0x1, 0x80, 0x5, 0x80, 0x5, 0x1, 0x8, 0x47, 0x1, 0x0, 0x6, 0x0, 0x6, 0x1, 0x10, 0x47, 0x1, 0x0, 0x7, 0x0, 0x7, 0x1, 0x10, 0x47, 0x1, 0x0, 0x8, 0x0, 0x8, 0x1, 0x10, 0x47, 0x1, 0x0, 0x10, 0x0, 0x10, 0x1, 0x80, 0x47, 0x1, 0x80, 0x11, 0x80, 0x11, 0x1, 0x40, 0x47, 0x1, 0x0, 0xfe, 0x0, 0xfe, 0x1, 0x2, 0x86, 0x9, 0x0, 0x1, 0x0, 0xfc, 0xbf, 0xfe, 0x0, 0x4, 0x0, 0x0, 0x86, 0x9, 0x0, 0x0, 0x0, 0x0, 0xf8, 0xff, 0x0, 0x0, 0x8, 0x0, 0x79, 0x0 }) } // // PS2K - PC Keyboard Controller // Device(PS2K) { Name(_HID,EISAID("PNP0303") /*0x0303d041*/) Name(_CRS, Buffer(0x16) {0x47, 0x1, 0x60, 0x0, 0x60, 0x0, 0x1, 0x1, 0x47, 0x1, 0x64, 0x0, 0x64, 0x0, 0x1, 0x1, 0x23, 0x2, 0x0, 0x1, 0x79, 0x0 }) } // // PS2M - PS/2-style Mouse Port // Device(PS2M) { Name(_HID,EISAID("PNP0F13") /*0x130fd041*/) Name(_CRS, Buffer(0x6) {0x23, 0x0, 0x10, 0x1, 0x79, 0x0 }) } Method(DFIN) { } OperationRegion(SIIO, SystemIO, 0x2e, 0x2) Field(SIIO, ByteAcc, Lock, Preserve) { INDX, 8, DATA, 8 } Mutex(MTIO, 0) Name(CDEV, 0xff) Method(REGR, 2) { Acquire(MTIO, 0xffff) If(LNot(LEqual(CDEV, Arg0))) { Store(Arg0, CDEV) Store(0x7, INDX) Store(Arg0, DATA) } Store(Arg1, INDX) Store(DATA, Local0) Release(MTIO) Return(Local0) } Method(REGW, 3) { Acquire(MTIO, 0xffff) If(LNot(LEqual(CDEV, Arg0))) { Store(Arg0, CDEV) Store(0x7, INDX) Store(Arg0, DATA) } Store(Arg1, INDX) Store(Arg2, DATA) Release(MTIO) } Method(STAT, 1) { Acquire(MTIO, 0xffff) Store(0x26, INDX) And(DATA, Arg0, Local0) Release(MTIO) Return(XOr(Local0, Arg0, )) } // // FDC - Floppy Controller // Device(FDC_) { Name(_HID,EISAID("PNP0700") /*0x0007d041*/) Method(_STA) { If(STAT(0x1)) { If(REGR(0x0, 0x30)) { Return(0xf) } Else { If(LEqual(OSTP, 0x0)) { // Unknown OS Return(0xb) } Else { Return(0xd) } } } Else { Return(0x0) } } Method(_DIS) { Store("===FDC _DIS===", Debug) REGW(0x0, 0x30, 0x0) } Name(CRSA, Buffer(0x18) {0x47, 0x1, 0xf0, 0x3, 0xf0, 0x3, 0x1, 0x6, 0x47, 0x1, 0xf7, 0x3, 0xf7, 0x3, 0x1, 0x1, 0x22, 0x40, 0x0, 0x2a, 0x4, 0x0, 0x79, 0x0 }) Method(_CRS) { CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x4, MAXA) CreateWordField(CRSA, 0xa, MINB) CreateWordField(CRSA, 0xc, MAXB) CreateWordField(CRSA, 0x11, INTA) CreateByteField(CRSA, 0x14, DMAB) If(REGR(0x0, 0x30)) { Store(_PRS, CRSA) } Else { If(LEqual(OSTP, 0x0)) { // Unknown OS Store(_PRS, CRSA) } Else { Store(Zero, MINA) Store(Zero, MAXA) Store(Zero, MINB) Store(Zero, MAXB) Store(Zero, INTA) Store(Zero, DMAB) } } Return(CRSA) } Name(_PRS, Buffer(0x18) {0x47, 0x1, 0xf0, 0x3, 0xf0, 0x3, 0x1, 0x6, 0x47, 0x1, 0xf7, 0x3, 0xf7, 0x3, 0x1, 0x1, 0x22, 0x40, 0x0, 0x2a, 0x4, 0x0, 0x79, 0x0 }) Method(_SRS, 1) { Store(Arg0, CRSA) CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x11, INTA) CreateByteField(CRSA, 0x14, DMAB) FindSetRightBit(INTA, Local0) If(Local0) { Decrement(Local0) } REGW(0x0, 0x70, Local0) FindSetRightBit(DMAB, Local0) If(Local0) { Decrement(Local0) } REGW(0x0, 0x74, Local0) ShiftRight(MINA, 0x8, Local0) REGW(0x0, 0x60, Local0) And(MINA, 0xff, Local0) REGW(0x0, 0x61, Local0) REGW(0x0, 0x30, One) } } Device(LPT_) { Name(FLAG, 0xff) Name(_PSC, 0x0) Method(MODE) { If(LEqual(FLAG, 0xff)) { If(STAT(0x2)) { ShiftRight(REGR(0x1, 0xf0), 0x5, Local0) If(LOr(LEqual(Local0, 0x4), LEqual(Local0, 0x7))) { Store(0x2, FLAG) } Else { Store(0x1, FLAG) } } Else { Store(0x0, FLAG) } } Return(FLAG) } // _HID - Hardware ID // // Supplies OSPM with the device's Plug and Play // hardware ID. When describing a platform, use of // any _HID objects is optional. However, a _HID // object must be used to describe any device that // will be enumerated by OSPM. OSPM only enumerates // a device when no bus enumerator can detect the // device ID. For example, devices on an ISA bus are // enumerated by OSPM. Use the _ADR object to // describe devices enumerated by bus enumerators // other than OSPM. // // IN: None // OUT: DeviceId EISAID or String giving the device // name Method(_HID) { If(LEqual(MODE(), 0x2)) { Return(0x0104d041) } Else { Return(0x0004d041) } } Method(_STA) { If(REGR(0x1, 0x30)) { Return(0xf) } Else { Return(0xd) } } Method(_DIS) { Store("===LPT _DIS===", Debug) REGW(0x1, 0x30, Zero) } Name(CRSA, Buffer(0xd) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x0, 0x0, 0x79, 0x0 }) Name(CRSB, Buffer(0x18) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x0, 0x0, 0x2a, 0x0, 0x0, 0x79, 0x0 }) Method(_CRS) { CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x4, MAXA) CreateWordField(CRSA, 0x9, INTA) Store(Zero, MINA) Store(Zero, MAXA) Store(Zero, INTA) CreateWordField(CRSB, 0x2, MINB) CreateWordField(CRSB, 0x4, MAXB) CreateWordField(CRSB, 0xa, MINC) CreateWordField(CRSB, 0xc, MAXC) CreateWordField(CRSB, 0x11, INTB) CreateByteField(CRSB, 0x14, DMAB) Store(Zero, MINB) Store(Zero, MAXB) Store(Zero, MINC) Store(Zero, MAXC) Store(Zero, INTB) Store(Zero, DMAB) If(REGR(0x1, 0x30)) { ShiftLeft(REGR(0x1, 0x60), 0x8, Local0) Add(Local0, REGR(0x1, 0x61), Local0) Store(Local0, MINA) Store(Local0, MAXA) Store(Local0, MINB) Store(Local0, MAXB) Add(Local0, 0x0400, Local0) Store(Local0, MINC) Store(Local0, MAXC) And(REGR(0x1, 0x70), 0xf, Local0) If(Local0) { ShiftLeft(One, Local0, Local0) } Store(Local0, INTA) Store(Local0, INTB) Store(REGR(0x1, 0x74), Local0) If(LNot(LEqual(Local0, 0x4))) { ShiftLeft(One, Local0, DMAB) } } If(LEqual(MODE(), 0x2)) { Return(CRSB) } Else { Return(CRSA) } } Name(PRSA, Buffer(0x1b) {0x30, 0x47, 0x1, 0x78, 0x3, 0x78, 0x3, 0x1, 0x8, 0x22, 0xa0, 0x0, 0x30, 0x47, 0x1, 0x78, 0x2, 0x78, 0x2, 0x1, 0x8, 0x22, 0xa0, 0x0, 0x38, 0x79, 0x0 }) Name(PRSB, Buffer(0x31) {0x30, 0x47, 0x1, 0x78, 0x3, 0x78, 0x3, 0x1, 0x8, 0x47, 0x1, 0x78, 0x7, 0x78, 0x7, 0x1, 0x8, 0x22, 0xa0, 0x0, 0x2a, 0xf, 0x0, 0x30, 0x47, 0x1, 0x78, 0x2, 0x78, 0x2, 0x1, 0x8, 0x47, 0x1, 0x78, 0x6, 0x78, 0x6, 0x1, 0x8, 0x22, 0xa0, 0x0, 0x2a, 0xf, 0x0, 0x38, 0x79, 0x0 }) Method(_PRS) { If(LEqual(MODE(), 0x2)) { Return(PRSB) } Else { Return(PRSA) } } Method(_SRS, 1) { If(LEqual(MODE(), 0x2)) { Store(Arg0, CRSB) CreateWordField(CRSB, 0x2, MINB) CreateWordField(CRSB, 0x11, INTB) CreateByteField(CRSB, 0x14, DMAB) FindSetRightBit(DMAB, Local0) If(Local0) { Decrement(Local0) } Else { Store(0x4, Local0) } Store(MINB, Local1) Store(INTB, Local2) } Else { Store(Arg0, CRSA) CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x9, INTA) Store(0x4, Local0) Store(MINA, Local1) Store(INTA, Local2) } REGW(0x1, 0x74, Local0) ShiftRight(Local1, 0x8, Local0) REGW(0x1, 0x60, Local0) And(Local1, 0xff, Local0) REGW(0x1, 0x61, Local0) FindSetRightBit(Local2, Local0) If(Local0) { Decrement(Local0) } REGW(0x1, 0x70, Local0) REGW(0x1, 0x30, 0x1) } Method(_PS0) { Store("===LPT _PS0===", Debug) Store(REGR(0x3, 0x30), Local0) REGW(0x3, 0x30, Local0) REGW(0x1, 0x30, 0x1) Store(0x0, _PSC) } Method(_PS3) { Store("===LPT _PS3===", Debug) Store(0x3, _PSC) } } // // COMA - 16550 Serial Port // Device(COMA) { Name(_HID,EISAID("PNP0501") /*0x0105d041*/) Name(_PSC, 0x0) Name(_RMV, 0x0) Name(SRSM, 0x0) Name(SCNT, 0x0) Method(_STA) { Store("===COMA _STA===", Debug) If(LEqual(\_SB_.PCI0.LPCB.EC0_.ECOK, 0x1)) { If(\_SB_.PCI0.LPCB.EC0_.CSPR) { REGW(0x3, 0x26, Zero) Store(REGR(0x3, 0x26), Local0) And(Local0, 0xf7, Local0) REGW(0x3, 0x26, Local0) If(REGR(0x3, 0x30)) { Store(0x1, \_SB_.PCI0.LPCB.CMAD) Return(0xf) } Else { Store(0x0, \_SB_.PCI0.LPCB.CMAD) Return(0xd) } } Else { If(LOr(SRSM, SCNT)) { Store(0x0, SRSM) Store(0x2, SCNT) If(REGR(0x3, 0x30)) { Store(0x1, \_SB_.PCI0.LPCB.CMAD) Return(0xf) } Else { Store(0x0, \_SB_.PCI0.LPCB.CMAD) Return(0xd) } } Else { Store(0x0, \_SB_.PCI0.LPCB.CMAD) Return(0x0) } } } Else { \_SB_.PCI0.LPCB.PHSS(0x7a) Store(\_SB_.PCI0.LPCB.INF_, Local1) If(LEqual(Local1, 0xa6)) { Store(0x1, \_SB_.PCI0.LPCB.CMAD) Return(0xd) } Else { Store(0x0, \_SB_.PCI0.LPCB.CMAD) Return(0x0) } } } Method(_DIS) { Store("===COMA _DIS===", Debug) REGW(0x3, 0x30, Zero) Store(0x0, \_SB_.PCI0.LPCB.CMAD) } Name(CRSA, Buffer(0xd) {0x47, 0x1, 0xf8, 0x3, 0xf8, 0x3, 0x1, 0x8, 0x22, 0x10, 0x0, 0x79, 0x0 }) Method(_CRS) { CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x4, MAXA) CreateWordField(CRSA, 0x9, INTA) If(REGR(0x3, 0x30)) { ShiftLeft(REGR(0x3, 0x60), 0x8, Local0) Add(Local0, REGR(0x3, 0x61), Local0) Store(Local0, MINA) Store(Local0, MAXA) And(REGR(0x3, 0x70), 0xf, Local0) If(Local0) { ShiftLeft(One, Local0, Local0) } Store(Local0, INTA) } Else { Store(Zero, MINA) Store(Zero, MAXA) Store(Zero, INTA) } Return(CRSA) } Name(_PRS, Buffer(0x33) {0x30, 0x47, 0x1, 0xf8, 0x3, 0xf8, 0x3, 0x1, 0x8, 0x22, 0x18, 0x0, 0x30, 0x47, 0x1, 0xf8, 0x2, 0xf8, 0x2, 0x1, 0x8, 0x22, 0x18, 0x0, 0x30, 0x47, 0x1, 0xe8, 0x3, 0xe8, 0x3, 0x1, 0x8, 0x22, 0x18, 0x0, 0x30, 0x47, 0x1, 0xe8, 0x2, 0xe8, 0x2, 0x1, 0x8, 0x22, 0x18, 0x0, 0x38, 0x79, 0x0 }) Method(_SRS, 1) { Store(Arg0, CRSA) CreateWordField(CRSA, 0x2, MINX) CreateWordField(CRSA, 0x9, INTX) ShiftRight(MINX, 0x8, Local0) REGW(0x3, 0x60, Local0) And(MINX, 0xff, Local0) REGW(0x3, 0x61, Local0) FindSetRightBit(INTX, Local0) If(Local0) { Decrement(Local0) } REGW(0x3, 0x70, Local0) REGW(0x3, 0x30, 0x1) } Method(_PS0) { Store("===COMA _PS0===", Debug) REGW(0x3, 0xf0, 0x82) REGW(0x3, 0x30, 0x1) Store(0x0, _PSC) Store(0x1, \_SB_.PCI0.LPCB.CMAD) } Method(_PS3) { Store("===COMA _PS3===", Debug) Store(0x3, _PSC) Store(0x0, \_SB_.PCI0.LPCB.CMAD) } } Device(COMB) { Name(FLAG, 0xff) Name(_PSC, 0x0) Method(MODE) { If(LEqual(FLAG, 0xff)) { If(STAT(0x4)) { If(LEqual(REGR(0x2, 0x74), 0x4)) { Store(0x3, FLAG) } Else { Store(0x4, FLAG) } } Else { Store(0x0, FLAG) } } Return(FLAG) } Method(_HID) { If(LEqual(MODE(), 0x4)) { Return(0x0160633a) } Else { Return(0x1005d041) } } Method(_STA) { If(LEqual(MODE(), 0x0)) { Return(0x0) } Else { If(REGR(0x2, 0x30)) { Return(0xf) } Else { Return(0xd) } } } Method(_DIS) { Store("===COMB _DIS===", Debug) REGW(0x2, 0x30, Zero) } Name(CRSA, Buffer(0xd) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x0, 0x0, 0x79, 0x0 }) Name(CRSB, Buffer(0x10) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x0, 0x0, 0x2a, 0x0, 0x0, 0x79, 0x0 }) Method(_CRS) { CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x4, MAXA) CreateWordField(CRSA, 0x9, INTA) Store(Zero, MINA) Store(Zero, MAXA) Store(Zero, INTA) CreateWordField(CRSB, 0x2, MINB) CreateWordField(CRSB, 0x4, MAXB) CreateWordField(CRSB, 0x9, INTB) CreateByteField(CRSB, 0xc, DMAB) Store(Zero, MINB) Store(Zero, MAXB) Store(Zero, INTB) Store(Zero, DMAB) If(REGR(0x2, 0x30)) { ShiftLeft(REGR(0x2, 0x60), 0x8, Local0) Add(Local0, REGR(0x2, 0x61), Local0) Store(Local0, MINA) Store(Local0, MAXA) Store(Local0, MINB) Store(Local0, MAXB) And(REGR(0x2, 0x70), 0xf, Local0) If(Local0) { ShiftLeft(One, Local0, Local0) } Store(Local0, INTA) Store(Local0, INTB) Store(REGR(0x2, 0x74), Local0) If(LNot(LEqual(Local0, 0x4))) { ShiftLeft(One, Local0, DMAB) } } If(LEqual(MODE(), 0x4)) { Return(CRSB) } Else { Return(CRSA) } } Name(PRSA, Buffer(0x33) {0x30, 0x47, 0x1, 0xf8, 0x3, 0xf8, 0x3, 0x1, 0x8, 0x22, 0x18, 0x0, 0x30, 0x47, 0x1, 0xf8, 0x2, 0xf8, 0x2, 0x1, 0x8, 0x22, 0x18, 0x0, 0x30, 0x47, 0x1, 0xe8, 0x3, 0xe8, 0x3, 0x1, 0x8, 0x22, 0x18, 0x0, 0x30, 0x47, 0x1, 0xe8, 0x2, 0xe8, 0x2, 0x1, 0x8, 0x22, 0x18, 0x0, 0x38, 0x79, 0x0 }) Name(PRSB, Buffer(0x3f) {0x30, 0x47, 0x1, 0xf8, 0x3, 0xf8, 0x3, 0x1, 0x8, 0x22, 0x18, 0x0, 0x2a, 0xf, 0x0, 0x30, 0x47, 0x1, 0xf8, 0x2, 0xf8, 0x2, 0x1, 0x8, 0x22, 0x18, 0x0, 0x2a, 0xf, 0x0, 0x30, 0x47, 0x1, 0xe8, 0x3, 0xe8, 0x3, 0x1, 0x8, 0x22, 0x18, 0x0, 0x2a, 0xf, 0x0, 0x30, 0x47, 0x1, 0xe8, 0x2, 0xe8, 0x2, 0x1, 0x8, 0x22, 0x18, 0x0, 0x2a, 0xf, 0x0, 0x38, 0x79, 0x0 }) Method(_PRS) { If(LEqual(MODE(), 0x4)) { Return(PRSB) } Else { Return(PRSA) } } Method(_SRS, 1) { If(LEqual(MODE(), 0x4)) { Store(Arg0, CRSB) CreateWordField(CRSB, 0x2, MINB) CreateWordField(CRSB, 0x9, INTB) CreateByteField(CRSB, 0xc, DMAB) FindSetRightBit(DMAB, Local0) If(Local0) { Decrement(Local0) } Else { Store(0x4, Local0) } Store(MINB, Local1) Store(INTB, Local2) } Else { Store(Arg0, CRSA) CreateWordField(CRSA, 0x2, MINA) CreateWordField(CRSA, 0x9, INTA) Store(0x4, Local0) Store(MINA, Local1) Store(INTA, Local2) } REGW(0x2, 0x74, Local0) ShiftRight(Local1, 0x8, Local0) REGW(0x2, 0x60, Local0) And(Local1, 0xff, Local0) REGW(0x2, 0x61, Local0) FindSetRightBit(Local2, Local0) If(Local0) { Decrement(Local0) } REGW(0x2, 0x70, Local0) REGW(0x2, 0x30, 0x1) If(LEqual(MODE(), 0x4)) { Or(REGR(0x2, 0xf0), 0x80, Local0) REGW(0x2, 0xf0, Local0) } } Method(_PS0) { Store("===COMB _PS0===", Debug) REGW(0x2, 0xf0, 0x82) REGW(0x2, 0x30, 0x1) Store(0x0, _PSC) } Method(_PS3) { Store("===COMB _PS3===", Debug) Store(0x3, _PSC) } } Name(LP60, 0x0) Name(LP61, 0x0) Name(LP70, 0x0) Name(LP71, 0x0) Name(LP74, 0x0) Name(LPF0, 0x0) Method(S3SV) { Store(REGR(0x1, 0x60), LP60) Store(REGR(0x1, 0x61), LP61) Store(REGR(0x1, 0x70), LP70) Store(REGR(0x1, 0x71), LP71) Store(REGR(0x1, 0x74), LP74) Store(REGR(0x1, 0xf0), LPF0) } Method(S3RS) { Store(0xff, CDEV) REGW(0x1, 0x60, LP60) REGW(0x1, 0x61, LP61) REGW(0x1, 0x70, LP70) REGW(0x1, 0x71, LP71) REGW(0x1, 0x74, LP74) REGW(0x1, 0xf0, LPF0) } // // ACAD - AC Adapter // Device(ACAD) { Name(_HID, "ACPI0003") // _PCL - Power Consumer List // // Evaluates to a list of device or bus names, each // powered by the power source device. Pointing to a // bus indicates that all devices under the bus are // powered bythe power source device. // Name(_PCL, Package(0x1) { \_SB_, }) // _PSR - Power Source // // Evaluates to current power source devices. Used // for the AC adapter and is located under the AC // adapter object in name space. Used to determine // if system is running off the AC adapter. // // IN: None // OUT: OnLine 0 = Off-Line, 1 = On-Line Method(_PSR) { Return(\_SB_.PCI0.LPCB.ACPW) } } Method(ECOK) { If(LEqual(\_SB_.PCI0.LPCB.EC0_.ECOK, 0x1)) { Return(0x1) } Else { Return(0x0) } } // // EC0 - ACPI Embedded Controller // Device(EC0_) { Name(_HID,EISAID("PNP0C09") /*0x090cd041*/) Name(_GPE, 0x1c) Name(ECOK, Zero) Name(_CRS, Buffer(0x12) {0x47, 0x1, 0x62, 0x0, 0x62, 0x0, 0x1, 0x1, 0x47, 0x1, 0x66, 0x0, 0x66, 0x0, 0x1, 0x1, 0x79, 0x0 }) // _REG - Region Availability // // The OS executes _REG control methods to inform // ACPI system firmware of a change in the // availability of an operation region. When an // operation region handler is unavailable, AML // cannot access data fields in that region. // (Operation region writes will be ignored and // reads will return indeterminate data.). // Except for the cases shown below, methods must // assume all operation regions inaccessible until // the _REG(RegionSpace, 1) method is executed. Once // _REG has been executed for a particular operation // region, indicating that the operation region // handler is ready, a method can access fields in // the operation region. Conversely, methods must // not access fields in operation regions when _REG // method execution has not indicated that the // operation region handler is ready. // The exceptions for this rule are: // // 1. OSPM must guarantee that the following // operation regions must always be accessible: // PCI_Config operation regions on a PCI root // bus containing a _BBN object. // I/O operation regions. // Memory operation regions when accessing // memory returned by the System Address Map // reporting interfaces. // 2. OSPM must make Embedded Controller operation // regions, accessed via the Embedded Controllers // described in ECDT, available before executing // any method. These operation regions may become // inaccessible after OSPM runs _REG(3, 0). // Place _REG in the same scope as operation region // declarations. The OS will run the _REG in a given // scope when the operation regions declared in that // scope are available for use. // Note: The OS only runs _REG methods that appear in // the same scope as operation region declarations // that use the operation region type that has just // been made available. // // IN: Arg0 OperationRegionType. 0 - Memory // 1 - I/O // 2 - PCI_Config // 3 - Embedded Controller // 4 - SMBus // 5 - CMOS // 6 - PCIBARTarget // 0x80-0xFF - OEM region space handler // Arg1 Connect. 0 = Disconnect, 1 = Connect // OUT: None Method(_REG, 2) { If(LEqual(Arg0, 0x3)) { Store(Arg1, ECOK) } } OperationRegion(ERAM, EmbeddedControl, 0x0, 0xff) Field(ERAM, ByteAcc, Lock, Preserve) { Offset(0x60), SMPR, 8, SMST, 8, SMAD, 8, SMCM, 8, SMD0, 256, BCNT, 8, SMAA, 8, Offset(0x90), CHGM, 16, CHGS, 16, CHGC, 16, CHGV, 16, CHGA, 16, BAL0, 1, BAL1, 1, BAL2, 1, BAL3, 1, Offset(0x9c), BEEP, 1, FAN1, 1, FAN2, 1, CRT_, 1, EXFD, 1, PHDD, 1, SHDD, 1, FDD_, 1, SBTN, 1, VIDO, 1, VOLD, 1, VOLU, 1, MUTE, 1, CONT, 1, BRGT, 1, HBTN, 1, S4S_, 1, SKEY, 1, BKEY, 1, Offset(0x9f), RSMA, 1, Offset(0xa1), CSPR, 1, , 6, FSPR, 1, Offset(0xa3), S0LD, 1, S3LD, 1, VGAQ, 1, PCMQ, 1, PCMR, 1, ADP_, 1, SYS6, 1, SYS7, 1, PWAK, 1, MWAK, 1, LWAK, 1, Offset(0xa5), FOT_, 8, FSD1, 8, FSD2, 8, Offset(0xb0), CTMP, 8, Offset(0xb8), BCTL, 6, BLED, 1, Offset(0xb9), BRTS, 8, Offset(0xbb), WLAT, 1, BTAT, 1, WLEX, 1, BTEX, 1, KLSW, 1, Offset(0xbe), RSMT, 16, //BPR0 - Battery Present Rate??? , 4, BMF0, 3, BTY0, 1, BST0, 8, BRC0, 16, BSN0, 16, BPV0, 16, BDV0, 16, BDC0, 16, BFC0, 16, GAU0, 8, Offset(0xd0), , 4, BMF1, 3, BTY1, 1, BST1, 8, BRC1, 16, BSN1, 16, BPV1, 16, BDV1, 16, BDC1, 16, BFC1, 16, GAU1, 8 } Method(_Q11) { // Fn+F1, Fn+F2 (LCD Bright +/-) Store("=====QUERY_11=====", Debug) If(\_SB_.PCI0.LPCB.EC0_.BRGT) { PHSS(0x8) Store(0x0, \_SB_.PCI0.LPCB.EC0_.BRGT) } } Method(_Q1C) { // Fn+F5 (LCD/CRT) Store("=====QUERY_1C=====", Debug) If(LAnd(\_SB_.PCI0.LPCB.EC0_.VIDO, LNot(\_SB_.PCI0.GRFX.VRSM))) { \_SB_.PCI0.GRFX.DSSW() Store(0x0, \_SB_.PCI0.LPCB.EC0_.VIDO) } } Method(_Q1A) { Store("=====QUERY_1A=====", Debug) If(LEqual(0x38731260, \_SB_.PCI0.PCIB.MIN2.LNID)) { If(LNot(LEqual(OSTP, 0x0))) { // Known OS // Notify 0x8B - // **** unknown object notifiation value Notify(\_SB_.PCI0.LPCB.HPCI, 0x8b) } } } Method(_Q22) { Store("=====QUERY_22=====", Debug) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) If(LNot(LEqual(OSTP, 0x0))) { // Known OS // Notify 0x86 - // **** unknown object notifiation value Notify(\_SB_.PCI0.LPCB.HPCI, 0x86) } } Method(_Q25) { Store("=====QUERY_25=====", Debug) Sleep(0x07d0) Store(0x0, RBIF) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) // Notify 0x81 - Control-Method Battery Information Changed (_BIF) Notify(\_SB_.PCI0.LPCB.BAT1, 0x81) } Method(_Q27) { Store("=====QUERY_27=====", Debug) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) If(LNot(LEqual(OSTP, 0x0))) { // Known OS // Notify 0x86 - // **** unknown object notifiation value Notify(\_SB_.PCI0.LPCB.HPCI, 0x86) } } Method(_Q2A) { Store("=====QUERY_2A=====", Debug) // Notify 0x01 - Device Check. Check device and parent Notify(\_SB_.PCI0.LPCB.COMA, 0x1) Store(0x0, \_SB_.PCI0.LPCB.EC0_.FSPR) } Method(_Q2B) { If(LNot(LOr(\_SB_.PCI0.LPCB.COMA.SCNT, \_SB_.PCI0.LPCB.COMA.SRSM))) { Store("=====QUERY_2B=====", Debug) // Notify 0x01 - Device Check. Check device and parent Notify(\_SB_.PCI0.LPCB.COMA, 0x1) Store(0x0, \_SB_.PCI0.LPCB.EC0_.FSPR) } Else { Decrement(\_SB_.PCI0.LPCB.COMA.SCNT) } } Method(_Q37) { // AC reconnect Store("=====QUERY_37=====", Debug) PHSS(0xd) Sleep(0x14) // Notify 0x80 - AC Adapter Status Changed Notify(\_SB_.PCI0.LPCB.ACAD, 0x80) Sleep(0x14) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) Sleep(0x14) // Notify 0x81 - Control-Method Battery Information Changed (_BIF) Notify(\_SB_.PCI0.LPCB.BAT1, 0x81) } Method(_Q38) { // AC disconnect Store("=====QUERY_38=====", Debug) PHSS(0xd) Sleep(0x14) // Notify 0x80 - AC Adapter Status Changed Notify(\_SB_.PCI0.LPCB.ACAD, 0x80) Sleep(0x14) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) Sleep(0x14) // Notify 0x81 - Control-Method Battery Information Changed (_BIF) Notify(\_SB_.PCI0.LPCB.BAT1, 0x81) } Method(_Q40) { Store("=====QUERY_40=====", Debug) PHSS(0x73) } Method(_Q41) { // Sleep Button Store("=====QUERY_41=====", Debug) // Notify 0x80 - Control-Method Sleep Button Pressed In S0 Notify(\_SB_.SLPB, 0x80) } Method(_Q42) { // Timer? (~1/min) Store("=====QUERY_42=====", Debug) PHSS(0x74) If(LEqual(OSTP, 0x0)) { // Unknown OS If(LAnd(BSOK, LEqual(RBIF, 0x0))) { // Notify 0x81 - Control-Method Battery Information Changed (_BIF) Notify(\_SB_.PCI0.LPCB.BAT1, 0x81) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) } } } } // // BAT1 - Control-Method Battery // Device(BAT1) { Name(_HID,EISAID("PNP0C0A") /*0x0a0cd041*/) Name(_UID, 0x1) Name(_PCL, Package(0x1) { \_SB_, }) Name(FUCC, 0x1518) Name(PBIF, Package(0xd) { 0x1, 0x1518, 0x1518, 0x1, 0x1fff, 0x021c, 0xa2, 0x0108, 0x0ec4, "LIP9071", " ", "LiON", "HP ", }) Name(PBST, Package(0x4) { 0x1, 0x0, 0x33, 0x1fff, }) Method(_STA) { // /proc/acpi/battery/BAT1/state (Battery State) read If(LAnd(\_SB_.PCI0.LPCB.EC0_.ECOK, LEqual(ECDY, 0x0))) { Store("==Battery _STA==", Debug) If(\_SB_.PCI0.LPCB.EC0_.BAL0) { Store(0x1, BSOK) Return(0x1f) } Else { Store(0x0, BSOK) Return(0xf) } } Else { Store(0x1, BSOK) Return(0x1f) } } // _BIF - Battery Information // // Returns the static portion of the Control Method // Battery information. Remains constant until the // battery is changed. The returned package has the // format: // // Entry Type Description // ---------------------------------------- // 0 Integer Battery power information in // 0=mW/mWh, 1=mA/mAh // 1 Integer Design capacity (mWh/mAh). Ones = // Unknown // 2 Integer Last full charge capacity (mWh/mAh). // Ones = Unknown // 3 Integer Battery technology. 0 = Non // -rechargeable, 1 = Rechargeable // 4 Integer Nominal new battery voltage (mV). // Ones = Unknown // 5 Integer Design capacity of Battery Warning // (mWh/mAh) // 6 Integer Design capacity of Battery Low // (mWh/mAh) // 7 Integer Battery capacity granularity between // Low and Warning (mWh/mAh) // 8 Integer Battery capacity granularity between // Warning and Full (mWh/mAh) // 9 String Model number // 10 String Serial number // 11 String Battery type // 12 String OEM information // // IN: None // OUT: BatteryInfo Static battery information Method(_BIF) { If(LAnd(\_SB_.PCI0.LPCB.EC0_.ECOK, LEqual(ECDY, 0x0))) { Store("==Battery _BIF==", Debug) Store(\_SB_.PCI0.LPCB.EC0_.BDC0, Local0) Store(Local0, Index(PBIF, 0x1, )) Store(\_SB_.PCI0.LPCB.EC0_.BFC0, Local2) Store(Local2, Index(PBIF, 0x2, )) Store(Local2, FUCC) Store(Local2, Local5) Store(Local2, Local6) Store(\_SB_.PCI0.LPCB.EC0_.BDV0, Index(PBIF, 0x4, )) Divide(Local5, 0x64, Local1, Local5) Multiply(Local5, 0xa, Local5) Store(Local5, Index(PBIF, 0x5, )) Divide(Local6, 0x64, Local1, Local6) Multiply(Local6, 0x3, Local6) Store(Local6, Index(PBIF, 0x6, )) Store(\_SB_.PCI0.LPCB.EC0_.BMF0, Local1) // Serial Number? Store(\_SB_.PCI0.LPCB.EC0_.BSN0, Index(PBIF, 0xa, )) // If(\_SB_.PCI0.LPCB.EC0_.BTY0) { If(LGreater(Local0, 0x0e10)) { If(LEqual(Local1, 0x1)) { Store("SI-CPL11", Index(PBIF, 0x9, )) } Else { If(LEqual(Local1, 0x2)) { Store("LIP9071", Index(PBIF, 0x9, )) } Else { Store("CGR-B/946AE", Index(PBIF, 0x9, )) } } } Else { If(LEqual(Local1, 0x2)) { Store("LIP6088", Index(PBIF, 0x9, )) } Else { Store("CGR-B/641AE", Index(PBIF, 0x9, )) } } Store("LiON", Index(PBIF, 0xb, )) } Else { Store("9HR-4/3AU", Index(PBIF, 0x9, )) Store("NiMH", Index(PBIF, 0xb, )) } Store(0x1, RBIF) } Return(PBIF) } // _BST - Battery Status // // Evaluates to a package containing the present // battery status. Whenever the Battery Status value // changes, the system will generate an SCI to // notify the OS. The returned package has the // format: // // Entry Type Description // ---------------------------------------- // 0 Integer Battery State: // [0] 1 = Discharging // [1] 1 = Charging // [2] 1 = Critical // Charging and Discharging // bits are mutually // exclusive // 1 Integer Battery Present Rate // (mWh/mAh) Ones = Unknown // 2 Integer Battery Remaining // Capacity (mWh/mAh) Ones = // Unknown // 3 Integer Battery Present Voltage // (mV) Ones = Unknown // // IN: None // OUT: BatteryStatus Battery level and status Method(_BST) { Store(DerefOf(Index(PBST, 0x2, )), Local2) Store(DerefOf(Index(PBST, 0x3, )), Local3) Store(FUCC, Local5) // Full Capacity If(LAnd(\_SB_.PCI0.LPCB.EC0_.ECOK, LEqual(ECDY, 0x0))) { Store("==Battery _BST==", Debug) Store(\_SB_.PCI0.LPCB.EC0_.BRC0, Local2) // Remaining Capacity Store(\_SB_.PCI0.LPCB.EC0_.BPV0, Local3) // Present Voltage Store(\_SB_.PCI0.LPCB.EC0_.GAU0, Local4) // Gauge (%) // Store(\_SB_.PCI0.LPCB.EC0_.BDC0, Local5) // Design Capacity Store(\_SB_.PCI0.LPCB.EC0_.BFC0, Local5) // Last Full Capacity } If(\_SB_.PCI0.LPCB.ACPW) { // On AC power Store(0x2, Local0) // charging // If(LEqual(Local2, Local5)) { // Store(0x0, Local0) // full ("unknown"?) // } } Else { // discharging Store(0x1, Local0) // discharging If(LEqual(Local2,0)) { Store(Or(Local0,0x4),Local0) // critical Multiply(Local4, FUCC, Local2) If(Local2) { Divide(Local2, 0x64, Local1, Local2) If(LNot(LGreater(Local4, 0x63))) { Increment(Local2) // ~Remaining Capacity } } } } Multiply(Local5, 0x3, Local5) Divide(Local5, 0x64, Local1, Local5) // Design Capacity Battery Low If(LGreater(Local5,Local2)) { Store(Or(Local0,0x4),Local0) // critical } Store(Local0, Index(PBST, 0x0, )) // Battery Present Rate -> unknown // Store(Ones, Index(PBST, 0x1, )) // Store(\_SB_.PCI0.LPCB.EC0_.BST0, Index(PBST, 0x1, )) // Present Rate Store(Local2, Index(PBST, 0x2, )) Store(Local3, Index(PBST, 0x3, )) If(LGreater(ECDY, 0x0)) { Decrement(ECDY) If(LEqual(ECDY, 0x0)) { // Notify 0x81 - Control-Method Battery Information Changed (_BIF) Notify(\_SB_.PCI0.LPCB.BAT1, 0x81) // Notify 0x80 - Control-Method Battery Status Changed (_BST) Notify(\_SB_.PCI0.LPCB.BAT1, 0x80) } } Return(PBST) } } Device(HPCI) { Name(_HID,EISAID("HWPC209") /*0x09c2f022*/) Name(Z000, 0x0) Method(STAT, 1) { Store(Arg0, Z000) } Method(_STA) { If(LNot(LEqual(OSTP, 0x0))) { // Known OS Return(0xf) } Else { Return(0x0) } } Method(GKBL) { Return(0xb) } Method(GDCP) { Return(0x0001000a) } Method(GDBT) { If(LEqual(\_SB_.PCI0.LPCB.EC0_.ECOK, 0x1)) { Store(\_SB_.PCI0.LPCB.EC0_.BRTS, Local0) Return(Local0) } Else { Return(0x0) } } Method(SDBT, 1) { If(LEqual(\_SB_.PCI0.LPCB.EC0_.ECOK, 0x1)) { Store(Arg0, Local0) And(Local0, 0xf, Local0) If(LGreater(Local0, 0xa)) { Store(0xa, Local0) } Store(Local0, \_SB_.PCI0.LPCB.EC0_.BRTS) } } Method(GADP) { \_SB_.PCI0.LPCB.PHSS(0x76) Store(\_SB_.PCI0.LPCB.INF_, Local0) Store(0x0, Local1) If(And(Local0, 0x8, )) { Or(Local1, 0x1, Local1) } If(And(Local0, 0x1, )) { Or(Local1, 0x2, Local1) } If(And(Local0, 0x2, )) { Or(Local1, 0x4, Local1) } \_SB_.PCI0.LPCB.PHSS(0x75) Store(\_SB_.PCI0.LPCB.INF_, Local0) If(And(Local0, 0x8, )) { Or(Local1, 0x10, Local1) } If(And(Local0, 0x1, )) { Or(Local1, 0x20, Local1) } If(And(Local0, 0x2, )) { Or(Local1, 0x40, Local1) } Return(Local1) } Method(SADP, 1) { Store(Arg0, Local0) And(Local0, 0xb, Local0) Store(0x0, Local1) If(And(Local0, 0x1, )) { Or(Local1, 0x8, Local1) } If(And(Local0, 0x2, )) { Or(Local1, 0x1, Local1) } If(And(Local0, 0x4, )) { Or(Local1, 0x2, Local1) } If(LEqual(Local0, 0xb)) { Store(0x9, Local1) } If(LEqual(0x0, DSEN)) { Store(Local1, \_SB_.PCI0.GRFX.NSTE) // Notify 0x80 - // **** unknown object notifiation value Notify(\_SB_.PCI0.GRFX, 0x80) } If(LEqual(0x1, DSEN)) { Store(Local1, \_SB_.PCI0.LPCB.INF_) \_SB_.PCI0.LPCB.PHSS(0x79) // Notify 0x81 - // **** unknown object notifiation value Notify(\_SB_.PCI0.GRFX, 0x81) } } Method(TGAD) { \_SB_.PCI0.GRFX.DSSW() } Method(GFPR) { \_SB_.PCI0.LPCB.PHSS(0x78) Store(\_SB_.PCI0.LPCB.INF1, Local0) Return(Local0) } Name(DDA0, Ones) Name(DDA1, Ones) Name(DDA2, Ones) Name(DDA3, Ones) Name(DDA4, Ones) Name(DDA5, Ones) Name(DDA6, Ones) Name(DDA7, Ones) Name(DDA8, Ones) Name(DDA9, Ones) Method(SRFL, 1) { If(ECOK()) { Store(Arg0, \_SB_.PCI0.LPCB.EC0_.BLED) } } } } Device(USB0) { Name(_ADR, 0x001d0000) OperationRegion(U0CS, PCI_Config, 0xc4, 0x4) Field(U0CS, DWordAcc, NoLock, Preserve) { U0EN, 2 } // _PRW - Power Resources for Wake // // Required for devices that have the ability to wake // the system from a system sleeping state. // Evaluates to a package of the following // definition: // // Entry Type Description // ---------------------------------------- // 0 Integer Event number in GPE block described // in the FADT used to enable the // wake event // . Package 0 = Name of GPE block device. 1 = // Event number in block // 1 Integer Lowest Sx state that can be entered // and still wake the system // 2+ Name Name of power resource which must // be ON in order to wake the system // // For OSPM to have the defined wake capability // properly enabled for the device, the following // must occur: // 1. All Power Resources referenced by elements 2 // through N are put into the ON state. // 2. If present, the _PSW method is executed to set // the device-specific registers to enable the // wake functionality of the device. // // Then, if the system wants to enter a sleeping // state: // 1. Interrupts are disabled. // 2. The sleeping state being entered must be // greater or equal to the power state declared // in element 1 of the _PRW object. // 3. The proper general-purpose register bits are // enabled. // // The system sleeping state specified must be a // state that the system supports (in other words, a // corresponding \_Sx object must exist in the // namespace). _PRW must evaluate to the same data // each time it is evaluated. All power resources // referenced must exist in the namespace. // // IN: None // OUT: ResourcePackage Array of Power Resource // information neededfor waking // the system Method(_PRW) { If(LGreater(OSTP, 0x1)) { // Some known OS (>ME) Return(Package(0x2) { 0x3, 0x1, }) } Else { Return(Package(0x2) { 0x3, 0x3, }) } } Method(_PSW, 1) { If(Arg0) { Store(0x3, U0EN) } Else { Store(0x0, U0EN) } } } Device(USB1) { Name(_ADR, 0x001d0001) OperationRegion(U1CS, PCI_Config, 0xc4, 0x4) Field(U1CS, DWordAcc, NoLock, Preserve) { U1EN, 2 } Method(_PRW) { If(LGreater(OSTP, 0x1)) { // Some known OS (>ME) Return(Package(0x2) { 0x4, 0x1, }) } Else { Return(Package(0x2) { 0x4, 0x3, }) } } Method(_PSW, 1) { If(Arg0) { Store(0x3, U1EN) } Else { Store(0x0, U1EN) } } } Device(USB2) { Name(_ADR, 0x001d0002) OperationRegion(U2CS, PCI_Config, 0xc4, 0x4) Field(U2CS, DWordAcc, NoLock, Preserve) { U2EN, 2 } Method(_PRW) { If(LGreater(OSTP, 0x1)) { // >ME Return(Package(0x2) { 0xc, 0x1, }) } Else { Return(Package(0x2) { 0xc, 0x3, }) } } Method(_PSW, 1) { If(Arg0) { Store(0x3, U2EN) } Else { Store(0x0, U2EN) } } } Device(IDEC) { Name(_ADR, 0x001f0001) OperationRegion(IDEC, PCI_Config, 0x40, 0x18) Field(IDEC, DWordAcc, NoLock, Preserve) { PRIT, 16, SECT, 16, PSIT, 4, SSIT, 4, Offset(0x8), SDMA, 4, Offset(0xa), SDT0, 2, , 2, SDT1, 2, Offset(0xb), SDT2, 2, , 2, SDT3, 2, Offset(0x14), ICR0, 4, ICR1, 4, ICR2, 4, ICR3, 4, ICR4, 4, ICR5, 4 } Device(PRID) { Name(_ADR, 0x0) OperationRegion(HDIO, SystemIO, 0x01f0, 0x8) Field(HDIO, ByteAcc, NoLock, Preserve) { Offset(0x1), Offset(0x2), Offset(0x3), Offset(0x4), Offset(0x5), Offset(0x6), HDSL, 8, HDCM, 8 } // _GTM - Get IDE Controller Timing // // Evaluates to the current settings for the IDE // channel. _GTM is listed under each channel device // object. The buffer has the following format: // // Offset Size Description // ---------------------------------------- // 0 4 PIO timing in ns for drive 0. // 0xFFFFFFFF = not supported // 4 4 DMA timing in ns for drive 0. // 0xFFFFFFFF = not supported // 8 4 PIO timing in ns for drive 1. // 0xFFFFFFFF = not supported // 12 4 DMA timing in ns for drive 1. // 0xFFFFFFFF = not supported // 16 4 Flags: // [0] 1 = Drive 0, Ultra-DMA // [1] 1 = Drive 0, IOChannelReady // [2] 1 = Drive 1, Ultra-DMA // [3] 1 = Drive 1, IOChannelReady // [4] 1 = Timing for each drive is // independent // // IN: None // OUT: TimingBuffer Drive 0/1 Timing Information Method(_GTM) { Return(Buffer(0x14) {0x78, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x78, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x1f, 0x0, 0x0, 0x0 }) Name(PBUF, Buffer(0x14) {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) CreateDWordField(PBUF, 0x0, PIO0) CreateDWordField(PBUF, 0x4, DMA0) CreateDWordField(PBUF, 0x8, PIO1) CreateDWordField(PBUF, 0xc, DMA1) CreateDWordField(PBUF, 0x10, FLAG) Store(GETP(PRIT), PIO0) Store(GETD(And(SDMA, 0x1, ), And(ICR3, 0x1, ), And(ICR0, 0x1, ), SDT0), DMA0) If(LEqual(DMA0, 0xffffffff)) { Store(PIO0, DMA0) } If(And(PRIT, 0x4000, )) { If(LEqual(And(PRIT, 0x90, ), 0x80)) { Store(0x0384, PIO1) } Else { Store(GETT(PSIT), PIO1) } } Else { Store(0xffffffff, PIO1) } Store(GETD(And(SDMA, 0x2, ), And(ICR3, 0x2, ), And(ICR0, 0x2, ), SDT1), DMA1) If(LEqual(DMA1, 0xffffffff)) { Store(PIO1, DMA1) } Store(GETF(And(SDMA, 0x1, ), And(SDMA, 0x2, ), PRIT), FLAG) Return(PBUF) } // _STM - Set IDE Controller Timing // // Sets the IDE channel's transfer timings to the // setting requested. The method is required to // convert and set the nanoseconds timing to the // appropriate transfer mode settings for the IDE // controller. _STM may also make adjustments so // that _GTF control methods return the correct // commands for the current channel settings. // // IN: Arg0 GTMInfo. Channel timing information returned by // _GTM // Arg1 Drive0Info. Raw data returned by the Identify Drive // ATA command (0xEC) for drive 0. // Arg2 Drive1Info. Raw data returned by the Identify Drive // ATA command (0xEC) for drive 1. // OUT: None Method(_STM, 3) { CreateDWordField(Arg0, 0x0, PIO0) CreateDWordField(Arg0, 0x4, DMA0) CreateDWordField(Arg0, 0x8, PIO1) CreateDWordField(Arg0, 0xc, DMA1) CreateDWordField(Arg0, 0x10, FLAG) Store(0x4, ICR2) If(LEqual(SizeOf(Arg1), 0x0200)) { And(PRIT, 0x40f0, PRIT) And(SDMA, 0xe, SDMA) Store(0x0, SDT0) And(ICR0, 0xe, ICR0) And(ICR1, 0xe, ICR1) And(ICR3, 0xe, ICR3) And(ICR5, 0xe, ICR5) CreateWordField(Arg1, 0x62, W490) CreateWordField(Arg1, 0x6a, W530) CreateWordField(Arg1, 0x7e, W630) CreateWordField(Arg1, 0x80, W640) CreateWordField(Arg1, 0xb0, W880) Or(PRIT, 0x8004, PRIT) If(LAnd(And(FLAG, 0x2, ), And(W490, 0x0800, ))) { Or(PRIT, 0x2, PRIT) } Or(PRIT, SETP(PIO0, W530, W640), PRIT) If(And(FLAG, 0x1, )) { Or(SDMA, 0x1, SDMA) Store(SETD(DMA0), SDT0) If(And(W880, 0x20, )) { Or(ICR5, 0x1, ICR5) } If(And(W880, 0x10, )) { Or(ICR1, 0x1, ICR1) } If(LLess(DMA0, 0x1e)) { Or(ICR3, 0x1, ICR3) } If(LLess(DMA0, 0x3c)) { Or(ICR0, 0x1, ICR0) } } } If(LEqual(SizeOf(Arg2), 0x0200)) { And(PRIT, 0x3f0f, PRIT) Store(0x0, PSIT) And(SDMA, 0xd, SDMA) Store(0x0, SDT1) And(ICR0, 0xd, ICR0) And(ICR1, 0xd, ICR1) And(ICR3, 0xd, ICR3) And(ICR5, 0xd, ICR5) CreateWordField(Arg2, 0x62, W491) CreateWordField(Arg2, 0x6a, W531) CreateWordField(Arg2, 0x7e, W631) CreateWordField(Arg2, 0x80, W641) CreateWordField(Arg2, 0xb0, W881) Or(PRIT, 0x8040, PRIT) If(LAnd(And(FLAG, 0x8, ), And(W491, 0x0800, ))) { Or(PRIT, 0x20, PRIT) } If(And(FLAG, 0x10, )) { Or(PRIT, 0x4000, PRIT) If(LGreater(PIO1, 0xf0)) { Or(PRIT, 0x80, PRIT) } Else { Or(PRIT, 0x10, PRIT) Store(SETT(PIO1, W531, W641), PSIT) } } If(And(FLAG, 0x4, )) { Or(SDMA, 0x2, SDMA) Store(SETD(DMA1), SDT1) If(And(W881, 0x20, )) { Or(ICR5, 0x2, ICR5) } If(And(W881, 0x10, )) { Or(ICR1, 0x2, ICR1) } If(LLess(DMA0, 0x1e)) { Or(ICR3, 0x2, ICR3) } If(LLess(DMA0, 0x3c)) { Or(ICR0, 0x2, ICR0) } } } } Device(P_D0) { Name(_ADR, 0x0) Method(_GTF) { Name(PIB0, Buffer(0xe) {0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef, 0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef }) CreateByteField(PIB0, 0x1, PMD0) CreateByteField(PIB0, 0x8, DMD0) If(And(PRIT, 0x2, )) { If(LEqual(And(PRIT, 0x9, ), 0x8)) { Store(0x8, PMD0) } Else { Store(0xa, PMD0) ShiftRight(And(PRIT, 0x0300, ), 0x8, Local0) ShiftRight(And(PRIT, 0x3000, ), 0xc, Local1) Add(Local0, Local1, Local2) If(LEqual(0x3, Local2)) { Store(0xb, PMD0) } If(LEqual(0x5, Local2)) { Store(0xc, PMD0) } } } Else { Store(0x1, PMD0) } If(And(SDMA, 0x1, )) { Store(Or(SDT0, 0x40, ), DMD0) If(And(ICR0, 0x1, )) { Add(DMD0, 0x2, DMD0) } If(And(ICR3, 0x1, )) { Store(0x45, DMD0) } } Else { Or(Subtract(And(PMD0, 0x7, ), 0x2, ), 0x20, DMD0) } Return(PIB0) } Name(_PSC, 0x0) Method(_PS0) { Store(0xa0, HDSL) While(And(HDCM, 0x80, )) { Sleep(0x5) } Store(0x0, _PSC) } Method(_PS3) { Store(0x3, _PSC) } } Device(P_D1) { Name(_ADR, 0x1) // _GTF - Get IDE Drive Task File // // Evaluates to a buffer containing the ATA commands // used to restore the drive to boot up defaults // (that is, the state of the drive after POST). The // buffer is an array with each element in the array // consisting of 7 8-bit register values (56 bits) // corresponding to ATA task registers 1F1 thru 1F7. // Each entry in the array defines a command to the // drive. After powering up the drive, the OS will // send these commands to the drive, in the order // specified. The IDE driver may modify some of the // feature commands or append its own to better tune // the drive for OSPM features before sending the // commands to the drive. // // IN: None // OUT: TaskFileBuffer Array of 7-byte values for 171 // -177 Method(_GTF) { Name(PIB1, Buffer(0xe) {0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef, 0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef }) CreateByteField(PIB1, 0x1, PMD1) CreateByteField(PIB1, 0x8, DMD1) If(And(PRIT, 0x20, )) { If(LEqual(And(PRIT, 0x90, ), 0x80)) { Store(0x8, PMD1) } Else { Add(And(PSIT, 0x3, ), ShiftRight(And(PSIT, 0xc, ), 0x2, ), Local0) If(LEqual(0x5, Local0)) { Store(0xc, PMD1) } Else { If(LEqual(0x3, Local0)) { Store(0xb, PMD1) } Else { Store(0xa, PMD1) } } } } Else { Store(0x1, PMD1) } If(And(SDMA, 0x2, )) { Store(Or(SDT1, 0x40, ), DMD1) If(And(ICR0, 0x2, )) { Add(DMD1, 0x2, DMD1) } If(And(ICR3, 0x2, )) { Store(0x45, DMD1) } } Else { Or(Subtract(And(PMD1, 0x7, ), 0x2, ), 0x20, DMD1) } Return(PIB1) } } Method(_PS0) { } Method(_PS3) { } } Device(SECD) { Name(_ADR, 0x1) // _GTM - Get IDE Controller Timing // // Evaluates to the current settings for the IDE // channel. _GTM is listed under each channel device // object. The buffer has the following format: // // Offset Size Description // ---------------------------------------- // 0 4 PIO timing in ns for drive 0. // 0xFFFFFFFF = not supported // 4 4 DMA timing in ns for drive 0. // 0xFFFFFFFF = not supported // 8 4 PIO timing in ns for drive 1. // 0xFFFFFFFF = not supported // 12 4 DMA timing in ns for drive 1. // 0xFFFFFFFF = not supported // 16 4 Flags: // [0] 1 = Drive 0, Ultra-DMA // [1] 1 = Drive 0, IOChannelReady // [2] 1 = Drive 1, Ultra-DMA // [3] 1 = Drive 1, IOChannelReady // [4] 1 = Timing for each drive is // independent // // IN: None // OUT: TimingBuffer Drive 0/1 Timing Information Method(_GTM) { Name(SBUF, Buffer(0x14) {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) CreateDWordField(SBUF, 0x0, PIO0) CreateDWordField(SBUF, 0x4, DMA0) CreateDWordField(SBUF, 0x8, PIO1) CreateDWordField(SBUF, 0xc, DMA1) CreateDWordField(SBUF, 0x10, FLAG) Store(GETP(SECT), PIO0) Store(GETD(And(SDMA, 0x4, ), And(ICR3, 0x4, ), And(ICR0, 0x4, ), SDT2), DMA0) If(LEqual(DMA0, 0xffffffff)) { Store(PIO0, DMA0) } If(And(SECT, 0x4000, )) { If(LEqual(And(SECT, 0x90, ), 0x80)) { Store(0x0384, PIO1) } Else { Store(GETT(SSIT), PIO1) } } Else { Store(0xffffffff, PIO1) } Store(GETD(And(SDMA, 0x8, ), And(ICR3, 0x8, ), And(ICR0, 0x8, ), SDT3), DMA1) If(LEqual(DMA1, 0xffffffff)) { Store(PIO1, DMA1) } Store(GETF(And(SDMA, 0x4, ), And(SDMA, 0x8, ), SECT), FLAG) Return(SBUF) } Method(_STM, 3) { CreateDWordField(Arg0, 0x0, PIO0) CreateDWordField(Arg0, 0x4, DMA0) CreateDWordField(Arg0, 0x8, PIO1) CreateDWordField(Arg0, 0xc, DMA1) CreateDWordField(Arg0, 0x10, FLAG) Store(0x4, ICR2) If(LEqual(SizeOf(Arg1), 0x0200)) { And(SECT, 0x40f0, SECT) And(SDMA, 0xb, SDMA) Store(0x0, SDT2) And(ICR0, 0xb, ICR0) And(ICR1, 0xb, ICR1) And(ICR3, 0xb, ICR3) And(ICR5, 0xb, ICR5) CreateWordField(Arg1, 0x62, W490) CreateWordField(Arg1, 0x6a, W530) CreateWordField(Arg1, 0x7e, W630) CreateWordField(Arg1, 0x80, W640) CreateWordField(Arg1, 0xb0, W880) Or(SECT, 0x8004, SECT) If(LAnd(And(FLAG, 0x2, ), And(W490, 0x0800, ))) { Or(SECT, 0x2, SECT) } Or(SECT, SETP(PIO0, W530, W640), SECT) If(And(FLAG, 0x1, )) { Or(SDMA, 0x4, SDMA) Store(SETD(DMA0), SDT2) If(And(W880, 0x20, )) { Or(ICR5, 0x4, ICR5) } If(And(W880, 0x10, )) { Or(ICR1, 0x4, ICR1) } If(LLess(DMA0, 0x1e)) { Or(ICR3, 0x4, ICR3) } If(LLess(DMA0, 0x3c)) { Or(ICR0, 0x4, ICR0) } } } If(LEqual(SizeOf(Arg2), 0x0200)) { And(SECT, 0x3f0f, SECT) Store(0x0, SSIT) And(SDMA, 0x7, SDMA) Store(0x0, SDT3) And(ICR0, 0x7, ICR0) And(ICR1, 0x7, ICR1) And(ICR3, 0x7, ICR3) And(ICR5, 0x7, ICR5) CreateWordField(Arg2, 0x62, W491) CreateWordField(Arg2, 0x6a, W531) CreateWordField(Arg2, 0x7e, W631) CreateWordField(Arg2, 0x80, W641) CreateWordField(Arg2, 0xb0, W881) Or(SECT, 0x8040, SECT) If(LAnd(And(FLAG, 0x8, ), And(W491, 0x0800, ))) { Or(SECT, 0x20, SECT) } If(And(FLAG, 0x10, )) { Or(SECT, 0x4000, SECT) If(LGreater(PIO1, 0xf0)) { Or(SECT, 0x80, SECT) } Else { Or(SECT, 0x10, SECT) Store(SETT(PIO1, W531, W641), SSIT) } } If(And(FLAG, 0x4, )) { Or(SDMA, 0x8, SDMA) Store(SETD(DMA1), SDT3) If(And(W881, 0x20, )) { Or(ICR5, 0x8, ICR5) } If(And(W881, 0x10, )) { Or(ICR1, 0x8, ICR1) } If(LLess(DMA0, 0x1e)) { Or(ICR3, 0x8, ICR3) } If(LLess(DMA0, 0x3c)) { Or(ICR0, 0x8, ICR0) } } } } Device(S_D0) { Name(_ADR, 0x0) Method(_GTF) { Name(SIB0, Buffer(0xe) {0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef, 0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef }) CreateByteField(SIB0, 0x1, PMD0) CreateByteField(SIB0, 0x8, DMD0) If(And(SECT, 0x2, )) { If(LEqual(And(SECT, 0x9, ), 0x8)) { Store(0x8, PMD0) } Else { Store(0xa, PMD0) ShiftRight(And(SECT, 0x0300, ), 0x8, Local0) ShiftRight(And(SECT, 0x3000, ), 0xc, Local1) Add(Local0, Local1, Local2) If(LEqual(0x3, Local2)) { Store(0xb, PMD0) } If(LEqual(0x5, Local2)) { Store(0xc, PMD0) } } } Else { Store(0x1, PMD0) } If(And(SDMA, 0x4, )) { Store(Or(SDT2, 0x40, ), DMD0) If(And(ICR0, 0x4, )) { Add(DMD0, 0x2, DMD0) } If(And(ICR3, 0x4, )) { Store(0x45, DMD0) } } Else { Or(Subtract(And(PMD0, 0x7, ), 0x2, ), 0x20, DMD0) } Return(SIB0) } } Device(S_D1) { Name(_ADR, 0x1) Method(_GTF) { Name(SIB1, Buffer(0xe) {0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef, 0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef }) CreateByteField(SIB1, 0x1, PMD1) CreateByteField(SIB1, 0x8, DMD1) If(And(SECT, 0x20, )) { If(LEqual(And(SECT, 0x90, ), 0x80)) { Store(0x8, PMD1) } Else { Add(And(SSIT, 0x3, ), ShiftRight(And(SSIT, 0xc, ), 0x2, ), Local0) If(LEqual(0x5, Local0)) { Store(0xc, PMD1) } Else { If(LEqual(0x3, Local0)) { Store(0xb, PMD1) } Else { Store(0xa, PMD1) } } } } Else { Store(0x1, PMD1) } If(And(SDMA, 0x8, )) { Store(Or(SDT3, 0x40, ), DMD1) If(And(ICR0, 0x8, )) { Add(DMD1, 0x2, DMD1) } If(And(ICR3, 0x8, )) { Store(0x45, DMD1) } } Else { Or(Subtract(And(PMD1, 0x7, ), 0x2, ), 0x20, DMD1) } Return(SIB1) } } Method(_PS0) { } Method(_PS3) { } } Method(GETP, 1) { If(LEqual(And(Arg0, 0x9, ), 0x0)) { Return(0xffffffff) } If(LEqual(And(Arg0, 0x9, ), 0x8)) { Return(0x0384) } ShiftRight(And(Arg0, 0x0300, ), 0x8, Local0) ShiftRight(And(Arg0, 0x3000, ), 0xc, Local1) Return(Multiply(0x1e, Subtract(0x9, Add(Local0, Local1, ), ), )) } Method(GETD, 4) { If(Arg0) { If(Arg1) { Return(0x17) } If(Arg2) { Return(Multiply(Subtract(0x4, Arg3, ), 0xf, )) } Return(Multiply(Subtract(0x4, Arg3, ), 0x1e, )) } Return(0xffffffff) } Method(GETT, 1) { Return(Multiply(0x1e, Subtract(0x9, Add(And(ShiftRight(Arg0, 0x2, ), 0x3, ), And(Arg0, 0x3, ), ), ), )) } Method(GETF, 3) { Name(TMPF, 0x0) If(Arg0) { Or(TMPF, 0x1, TMPF) } If(And(Arg2, 0x2, )) { Or(TMPF, 0x2, TMPF) } If(Arg1) { Or(TMPF, 0x4, TMPF) } If(And(Arg2, 0x20, )) { Or(TMPF, 0x8, TMPF) } If(And(Arg2, 0x4000, )) { Or(TMPF, 0x10, TMPF) } Return(TMPF) } Method(SETP, 3) { If(LNot(LLess(Arg0, 0xf0))) { Return(0x8) } Else { If(And(Arg1, 0x2, )) { If(LAnd(LNot(LGreater(Arg0, 0x78)), And(Arg2, 0x2, ))) { Return(0x2301) } If(LAnd(LNot(LGreater(Arg0, 0xb4)), And(Arg2, 0x1, ))) { Return(0x2101) } } Return(0x1001) } } Method(SETD, 1) { If(LNot(LGreater(Arg0, 0x17))) { Return(0x1) } If(LNot(LGreater(Arg0, 0x1e))) { Return(0x2) } If(LNot(LGreater(Arg0, 0x2d))) { Return(0x1) } If(LNot(LGreater(Arg0, 0x3c))) { Return(0x2) } If(LNot(LGreater(Arg0, 0x5a))) { Return(0x1) } Return(0x0) } Method(SETT, 3) { If(And(Arg1, 0x2, )) { If(LAnd(LNot(LGreater(Arg0, 0x78)), And(Arg2, 0x2, ))) { Return(0xb) } If(LAnd(LNot(LGreater(Arg0, 0xb4)), And(Arg2, 0x1, ))) { Return(0x9) } } Return(0x4) } } Device(SBUS) { Name(_ADR, 0x001f0003) } } } }